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Nirav Patel

Intern

SoC Design Engineer

Phoenix, Arizona Area

Section title

Nirav Patel's Email Addresses & Phone Numbers

Nirav Patel's Work Experience

Twin Antenna

Intern

January 2007 to May 2007

Vadodara, India

Intel Corporation

SoC Design Engineer

Chandler,AZ

Microchip Technology

Design Engineer

April 2012 to October 2015

Chandler, AZ

Nirav Patel's Education

San Jose State University

Master of Science (MS), Electrical Engineer

2008 to 2010

Hemchandracharya North Gujarat University

Bachelor of Engineering - BE, Electronics & Communication

2003 to 2007

Nirav Patel's Professional Skills Radar Chart

Based on our findings, Nirav Patel is ...

Inspiring
Matter-of-fact
Complex

What's on Nirav Patel's mind?

Based on our findings, Nirav Patel is ...

56% Left Brained
44% Right Brained

Nirav Patel's Estimated Salary Range

About Nirav Patel's Current Company

Twin Antenna

Frequently Asked Questions about Nirav Patel

What company does Nirav Patel work for?

Nirav Patel works for Twin Antenna


What is Nirav Patel's role at Twin Antenna?

Nirav Patel is Intern


What is Nirav Patel's personal email address?

Nirav Patel's personal email addresses are e****[email protected], and n****[email protected]


What is Nirav Patel's business email address?

Nirav Patel's business email addresses are not available


What is Nirav Patel's Phone Number?

Nirav Patel's phone (602) ***-*473


What industry does Nirav Patel work in?

Nirav Patel works in the Semiconductors industry.


About Nirav Patel

📖 Summary

Intern @ Twin Antenna From January 2007 to May 2007 (5 months) Vadodara, IndiaSoC Design Engineer @ Intel Corporation Chandler,AZDesign Engineer @ Microchip Technology • Responsibilities include digital IP top-level integration and RTL and gate-level verification.• Verification lead responsibilities include verification schedule development, assignment and monitoring of tasks to team members, reporting project verification status to product team and management • Experience with ECO flow for fixing control logic and datapath bugs. Formally verify the fixes using Synopsys Formality at full-chip level for equivalence checking of RTL to Gate level design.• Coordinate with the IP Design & Verification team and Architect on design issues and bug fixes. • Generate patterns using custom tool for production testing of silicon on Tester.• Debug failures, run regression and modify/develop tests as per requirements.• Hands on working experience of SystemVerilog Environment.• Working experience of various protocol integration and verification like I2C, ICAP, OCMP, UART etc• Provide support to cross-functional product teams (Product/Test, Architecture, Applications and Development Systems) to successfully release new PIC microcontroller families to production. From April 2012 to October 2015 (3 years 7 months) Chandler, AZStudent Assistant @ San Jose State University From September 2008 to December 2008 (4 months) San Jose, CA


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Nirav Patel's Personality Type

Introversion (I), Intuition (N), Thinking (T), Judging (J)

Average Tenure

1 year(s), 5 month(s)

Nirav Patel's Willingness to Change Jobs

Unlikely

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