Liang Zhou's Email & Phone Number

💼 Past Experience

Liang Zhou has over 5 years of experience in design and verification of CPUs, GPUs, ASICs, and memory devices. He began his career at AMD in February 2013 as a GPU Design #1 L1 TLB #2 L2 Texture Cache #3 L2 Texture Cache Interconnect Arbiter. Liangzhou was promoted to Senior RTL Design Engineer at Juniper Networks in February 2018.

🎓 Education

Liang Zhou's Educational Background:Liang Zhou has a Bachelor of Engineering (BEng), Telecommunication Engineering at Hubei University from 2003 to 2007. Liangzhou then earned a Doctor of Engineering (PHD), Electrical Engineering at the University of Arkansas at Fayetteville from 2008 to 2012.Liang Zhou's current educational trajectory begins with his college education where he earned a Bachelor of Engineering (BEng), Telecommunication Engineering at Hubei University from 2003 to 2007. Liangzhou then earned a Doctor of Engineering (PHD), Electrical Engineering at the University of Arkansas at Fayetteville from 2008 to 2012.Liang Zhou's professional experience includes a brief time as a research engineer with a definitive focus on wireless technology before transitioning into professional work as an electrical engineer with a 4.0/4.0 GPA at the University of Arkansas at Fayetteville. Liangzhou's work with university students has placed him in close proximity to some of the world's top engineers, who have supported Liangzhou's development as a researcher and engineer.

💡 Technical & Interpersonal Skills

Liang Zhou has over 15 years of experience in ASIC design, verification, and debugging. He has worked on a number of different ASIC designs at AMD, Juniper Networks, and NVIDIA. Liangzhou has a degree in Electrical and Computer Engineering from Sichuan University.