System, Serdes, Clock and ADCs.
Architect @ From September 2015 to Present (4 months) Sr. Analog Design Engineer @ Serdes, Clock. From September 2011 to August 2015 (4 years) Sr. Analog/Mixed Signal Designer @ Serdes, PLL. From September 2005 to September 2011 (6 years 1 month)
Guangmao Xing is skilled in: PLL, SERDES, PCIe, ADCs, SATA, DLL,