Satheesh Para
Sr. Manager - Silicon Design Engineering at AMD | Canada
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Sr. Manager - Silicon Design Engineering at AMD in August 2022 to Present
SOC Design Manager at Intel Corporation in July 2018 to August 2022
Senior Manager - ASIC Verification at IDT - Integrated Device Technology, Inc. in January 2009 to January 2018
Manager, ASIC Verification at Tundra Semiconductor in January 2002 to January 2009
Verification Lead at Accelight Networks Inc in May 2000 to June 2002
Senior ASIC Design/Verification Engineer at Tundra Semiconductor in January 1994 to January 2000
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University of Waterloo, BSc
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ASIC
Verilog
IC
FPGA
Functional Verification
Semiconductors
SoC
RTL design
SystemVerilog
EDA
Debugging
Perl
TCL
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Discover more about AMDWhat is Satheesh Para email address?
Email Satheesh Para at [email protected] and [email protected]. This email is the most updated Satheesh Para's email found in 2026.
How to contact Satheesh Para?
To contact Satheesh Para send an email to [email protected] or [email protected]. (updated on September 29, 2024)
What company does Satheesh Para work for?
Satheesh Para works for AMD
What is Satheesh Para's role at AMD?
Satheesh Para is Sr. Manager - Silicon Design Engineering
What is Satheesh Para's Phone Number?
Satheesh Para's phone (416) ***-*344
What industry does Satheesh Para work in?
Satheesh Para works in the Semiconductors industry.
Satheesh Para Email Addresses
Satheesh Para Phone Numbers
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