Vipul Chawla's Email

o Accomplished product and technology thinker/leader with 8 years of experience in designing wireless products. o Co-founded a startup and developed wireless motes, embedded wireless networking stack and sensing/monitoring applications.. o Product life-cycle experience of Wi-Fi SOCs - 802.11ac and 802.11n - IC design, systems, reference design, hardware debug. Specialties: Good understanding WiFi transceivers - IC design, systems, reference design, hardware debug. Strong IP core Implementation skills. Good software programming skills.

Staff Engineer - RF/Analog @ RF/Analog Design o Design lead of Wi-Fi receiver for the first 802.11ac MIMO SoC in 40 nm CMOS – revisited transceiver architecture and implemented the design from scratch. o Implemented and performed layout of various Rx circuits such as 2G/5G LNAs, RF Transconductor, Mixer, IM2 Calibration, Baseband Filters, Buffers and Bias blocks in 40 nm and 55 nm CMOS processes. o Proposed and implemented a dual-band Rx topology which helped reduce Rx silicon area by more than 50%. o Designed RF-PLL for a Bluetooth transceiver as part of a Wi-Fi combo chip in 40 nm CMOS. o Designed 10 GHz VCO, CML & CMOS Frequency Dividers, LO distribution and performed PLL noise, stability and settling time analysis. o Designed LNA and T/R switch in SOI CMOS process for the first dedicated frontend chip done in QCA for Wi-Fi transceivers. o EM simulations of various on-chip RF structures in Peakview and HFSS. o Designed complex baseband biquad filter, op-amps and ADC buffer for GPS & GLONASS receiver in 55 nm CMOS process. Systems o System level analysis and design of receiver gain lineup, noise and linearity budgets for 802.11 n/ac Wi-Fi transceiver. o Worked on lab bring-up of 2 generations - 802.11n and 11ac QCA Wi-Fi SoCs - performed characterization of receivers and PLLs, provided guidance on test procedures and enabled test teams by creating automation scripts in Perl. o Worked on complex system level debugs such as Wi-Fi end-point connection drop, system hang, DPLL locking failure, IQ calibration convergence, LO leakage, spurious pickup and DC offset. o Experience in debugging ESD and burn-in failures. o Worked with systems, software, reliability and testing teams across geographies, driving test and debug of transceivers, PLLs and PMU. From May 2011 to Present (4 years 6 months) San Francisco Bay AreaRF/Analog Design Engineer @ From March 2010 to May 2011 (1 year 3 months) Analog Design Engineer @ From December 2009 to March 2010 (4 months) RF/Mixed Signal Design Intern @ o Proposed and taped-out a new circuit topology for 10 GHz transformer based VCO/Divide-by-two in TSMC 65 nm. o Designed and implemented a closed loop power control circuit for WLAN transmitter output power control. From May 2008 to April 2009 (1 year) GRA @ o Explored a new paradigm of chip-to-chip communication using power supply network - an SRC funded project. o Designed and taped-out a receiver for Power Line Communications in microprocessors in IBM 130 nm CMOS process. o MATLAB based modeling of the communication system and estimation of BER. o RF PCB design using ADS Layout and Momentum for testing the data-recovery block IC chip. o Research and study on RFID circuits and implemented digital controller for EPC Class 1 RFID in VHDL. From June 2007 to May 2008 (1 year) Co-founder @ Founded a high-tech startup company in the field of wireless sensor networks (WSN), along with three other alumni of IIT Delhi. The startup was incubated in the business incubator of IITD. The company developed a versatile and proprietary hardware and software platform for WSN. With a licensing based business model, we worked with interested parties for development of WSN based applications. Example applications which were developed are production line monitoring for garment industry and home monitoring and security. The company also undertook industry projects in order to generate cash flows. Highlights of the work at Elfsys: o Core Product Development - Designed hardware for battery operated wireless motes, worked on development of proprietary embedded networking stack for wireless sensor networks, prototyped product applications. o Undertaking 3rd Party Industry Projects - Developed project proposals – system level design, resource planning and man-power/equipment budgeting, designed VHDL cores for a correlator system with sub-blocks like FFT, matrix multiplication, RAM interfaces etc on Virtex-IV FPGAs. o Business Development - Worked on business plan; held discussions with investors to secure seed and angel funding, defined product roadmap for both hardware and software, prepared demos and presented at trade-shows. From June 2004 to July 2006 (2 years 2 months)

M.S. @ Virginia Polytechnic Institute and State University From 2006 to 2009 B.Tech @ Indian Institute of Technology, Delhi From 2000 to 2004 Vipul Chawla is skilled in: VLSI, ASIC, SoC, Verilog, Analog Circuit Design, IC, CMOS, Mixed Signal, Circuit Design, Analog, RTL design, FPGA, Integrated Circuit..., VHDL, Signal Processing, Semiconductors, Simulations, RF, C, Embedded Systems, Debugging, Wireless