Guanlin Zhang’s Email & Phone

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Guanlin Zhang

Lead Analog/Mixed-signal design in 28Gbs SerDes for Stratix/Arria10 FPGA, PLL/CDR/CTLE/VGA @ Intel Corporation

Guanlin Zhang Contact Details

Location:
Santa Clara, California
Work:
Lead Analog/Mixed-signal design in 28Gbs SerDes for Stratix/Arria10 FPGA, PLL/CDR/CTLE/VGA @ Intel Corporation
Senior Staff Hardware Developer @ Oracle
Education:
@ Nanjing University
About:

Designed a novel charge-pump for low-power low-jitter 17GHz PLL in TSMC 40nm CMOS Based on current steering buffer to reduce switching and settling time Minimized UP/DOWN current mismatch within 1% by increasing output impedance with gain boosting circuits Designed a low-power low-jitter 17G/8G/2.5GHz PLL in TSMC 40nm CMOS for 2.5-17Gb/s SerDes for silicon photonic applications Leveraged Verilog-A 

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