Verilog

ASIC

C, C++

Labview

FPGA

RTL design

Timing Closure

Primetime

ASIC

Verilog

C++

Matlab

Functional Verification

VLSI

DDR3

Memory Controllers

ASIC

VLSI

SoC

RTL design

SystemVerilog

AHB

ASIC

SystemVerilog

Hardware

FPGA

VLSI

Verilog

RTL design

Computer Architecture

ASIC

RTL design

Microprocessors

Hardware Architecture

Integrated Circuit Design

Mixed Signal

FPGA

SERDES

ASIC/SOC Design/Verification, verilog, Systemverilog, ARM Assembly, C, perl

Verilog

ASIC

SystemVerilog

FPGA

ModelSim

Functional Verification

Debugging