Sebastien Gaubert

Sebastien Gaubert is a seasoned professional specializing in Analog, Memory, and Standard Cells Layout at Dolphin Integration, a leading provider of innovative solutions in the semiconductor industry. With a robust expertise in ASIC physical implementation, Sebastien plays a pivotal role in designing and optimizing complex integrated circuits, ensuring high performance and power efficiency. His current responsibilities encompass a broad spectrum of tasks, including the layout design of memory blocks and standard cells, which are critical for achieving optimal circuit density and functionality in advanced SoC architectures.

Sebastien is deeply involved in the development of design flows, utilizing TCL scripting to streamline simulation, characterization, and placement & routing (P&R) processes. His proficiency in EDA tools development enables him to create custom scripts for SOC power management, significantly enhancing the efficiency of power-aware design methodologies. Additionally, his expertise extends to modeling circuits in Verilog-AMS and SPICE, facilitating accurate behavioral and circuit-level simulations essential for verifying analog and mixed-signal blocks.

In his role, Sebastien also contributes to AMS verification, writing voltage regulator models and developing RTL-to-GDSII flow processes. His comprehensive understanding of the entire ASIC design cycle—from circuit modeling to physical implementation—allows him to optimize the integration of analog and digital components within complex SoCs. With skills spanning semiconductor physics, integrated circuit design, and microelectronics, Sebastien Gaubert continues to drive innovation in the field, leveraging his extensive knowledge of SPICE, Verilog, and power management techniques to deliver cutting-edge solutions in the semiconductor industry.