Nathan Kistner
Senior ASIC Floorplan Design Engineer at NVIDIA | Los Angeles Metropolitan Area
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Nathan Kistner is a Senior ASIC Floorplan Design Engineer at NVIDIA, where he plays a pivotal role in the physical design and optimization of cutting-edge semiconductor chips. With a strong foundation in physical design methodologies, Nathan specializes in the complete integration flow at both the macro and chip levels, focusing on critical areas such as floorplanning, place and route, clocking, and timing closure. His expertise is instrumental in driving the area review process, where he collaborates closely with architects, design leads, and package leads to craft and optimize floorplans during the early stages of chip development.
At NVIDIA, Nathan is actively engaged in key projects that push the boundaries of performance and efficiency in Application-Specific Integrated Circuits (ASIC). He leverages his skills in Verilog, MATLAB, and TCL to build scripts that automate various aspects of the design process, significantly enhancing productivity and accuracy. His proficiency with tools like Synopsys IC Compiler II and IBM Chipbench allows him to identify and implement improvements in area, interconnect, and floorplan design, ensuring that the final product meets stringent performance and timing requirements.
Nathan's ability to communicate effectively with cross-functional teams is crucial in solving complex design challenges and managing deliverables. His commitment to continuous improvement and innovation within the physical design domain not only contributes to the success of his projects but also positions him as a valuable asset in the fast-evolving semiconductor industry. As he continues to drive optimization efforts at NVIDIA, Nathan remains dedicated to advancing the capabilities of ASIC technology, ultimately shaping the future of high-performance computing.
Senior ASIC Floorplan Design Engineer at NVIDIA in May 2024 to Present
ASIC Physical Design Engineer III at NASA Jet Propulsion Laboratory in February 2020 to May 2024
SoC Back-End Design Engineer at Intel Corporation in June 2018 to February 2020
Hardware Integration/Physical Design Engineer at IBM in June 2015 to June 2018
Hardware Characterization Engineer at IBM in March 2017 to August 2017
Project Assistant (under the direction of Professor Eby G. Friedman) at University of Rochester in June 2014 to December 2014
Undergraduate Intern at University of Rochester in June 2013 to May 2014
Workshop Leader at University of Rochester in January 2013 to May 2013
Teacher's Assistant at University of Rochester in January 2012 to May 2012
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University of Rochester, Bachelor of Science (B.S.), September 2026
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Industry standards
C++
Cadence Virtuoso
Low-power Design
PHY
UPF
DFT
Static Timing Analysis
Logic Synthesis
Hardware Description Language
Logic Design
Timing
Place & Route
Layout Versus Schematic (LVS)
Design Rule Checking (DRC)
Verilog
Very-Large-Scale Integration (VLSI)
Matlab
VHDL
SPICE
SQL
Python
TCL
IBM Chipbench
Perl
Synopsys IC Compiler II
Bash
Printed Circuit Board (PCB) Design
System on a Chip (SoC)
Physical Design
Application-Specific Integrated Circuits (ASIC)
Cadence SKILL
C
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Discover more about NVIDIAWhat is Nathan Kistner email address?
Email Nathan Kistner at [email protected], [email protected] and [email protected]. This email is the most updated Nathan Kistner's email found in 2026.
What is Nathan Kistner phone number?
Nathan Kistner phone number is 2153601358 and 8143605480.
How to contact Nathan Kistner?
To contact Nathan Kistner send an email to [email protected], [email protected] or [email protected]. If you want to call Nathan Kistner try calling on 2153601358 and 8143605480. (updated on September 02, 2024)
What company does Nathan Kistner work for?
Nathan Kistner works for NVIDIA
What is Nathan Kistner's role at NVIDIA?
Nathan Kistner is Senior ASIC Floorplan Design Engineer
What industry does Nathan Kistner work in?
Nathan Kistner works in the Computer Hardware industry.
Nathan Kistner Email Addresses
Nathan Kistner Phone Numbers
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