Laurene Yip
Sr. Staff Packaging Engineer at Xilinx | San Francisco Bay Area
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Sr. Staff Packaging Engineer at Xilinx in June 2004 to Present
Manager - Package Development and Assembly Engineering at Celeritek Inc in November 1999 to November 2002
Staff Packaging Engineer at Philips Semiconductor in August 1992 to November 1999
Staff Product Engineer at VLSI Technology in July 1989 to August 1992
Staff Technologist at Bell Communications Research in June 1988 to August 1988
Research Engineer at Intel Corporation in June 1987 to January 1988
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University of California, Berkeley, Bachelor's degree
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Product Development
Program Management
New Product Implementations
Flip Chip
Electronic Packaging
Board Level Reliability
System Level Reliability
Power Cycling
3D IC Packaging
Root Cause Analysis
Failure Analysis
Electronics
Application-Specific Integrated Circuits (ASIC)
Engineering
Testing
Radio Frequency (RF)
Statistical Process Control (SPC)
Reliability
Materials
Yield
Design of Experiments
Integrated Circuits (IC)
Semiconductors
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Discover more about XilinxWhat is Laurene Yip email address?
Email Laurene Yip at [email protected]. This email is the most updated Laurene Yip's email found in 2026.
How to contact Laurene Yip?
To contact Laurene Yip send an email to [email protected]. (updated on September 07, 2024)
What company does Laurene Yip work for?
Laurene Yip works for Xilinx
What is Laurene Yip's role at Xilinx?
Laurene Yip is Sr. Staff Packaging Engineer
What is Laurene Yip's Phone Number?
Laurene Yip's phone (**) *** *** 360
What industry does Laurene Yip work in?
Laurene Yip works in the Semiconductors industry.
Laurene Yip Email Addresses
Laurene Yip Phone Numbers
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