Jixiang D
Senior ASIC Design verification engineer at 新思科技股份有限公司 | Ann Arbor, Michigan, United States
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Senior ASIC Design verification engineer at 新思科技股份有限公司 in January 2023 to Present
ASIC Design verification Engineer at Synopsys Inc in May 2022 to August 2022
Design Verification Engineer Intern at cisco in April 2021 to July 2021
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University of Michigan, Master of science, July 2026
Sichuan University, July 2026
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ASIC
Verilog
SystemVerilog
Universal Verification Methodology (UVM)
C 语言
通用验证方法学
SystemVerilog 语言
Linux
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What is Jixiang D email address?
Email Jixiang D at [email protected]. This email is the most updated Jixiang D's email found in 2026.
How to contact Jixiang D?
To contact Jixiang D send an email to [email protected]. (updated on August 26, 2024)
What company does Jixiang D work for?
Jixiang D works for 新思科技股份有限公司
What is Jixiang D's role at 新思科技股份有限公司?
Jixiang D is Senior ASIC Design verification engineer
What is Jixiang D's Phone Number?
Jixiang D's phone (313) ***-*300
What industry does Jixiang D work in?
Jixiang D works in the Computer Hardware industry.
Jixiang D Email Addresses
Jixiang D Phone Numbers
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