Over 25 year career as a Hardware Design Engineer specializing in FPGA, ASIC and embedded systems design with extensive system testing and debug experience. Digital circuit board design and embedded processor software development experience. Excellent problem solving skills covering all stages of the design cycle from architectural conception through prototype and production system testing and support. Recognized
Over 25 year career as a Hardware Design Engineer specializing in FPGA, ASIC and embedded systems design with extensive system testing and debug experience. Digital circuit board design and embedded processor software development experience. Excellent problem solving skills covering all stages of the design cycle from architectural conception through prototype and production system testing and support. Recognized for solving difficult problems at critical stages leading to numerous successful and profitable projects for the customer.
Specialties: Electronic Hardware design, testing and debug of prototype and production systems, FPGA & ASIC technology, embedded systems and software
Active Top Secret Security clearance
Principal Digital Design Engineer @ Lead digital engineer for beam steering project, including design of controller circuit board with FPGA controlling various RF components for time delay and amplitude adjustments and power regulation. Use of Altera Arria II GX FPGA, Nios II embedded processor and Max V CPLD for interactive control using message protocol over an RS-485 interface. Used Matlab for control interface with various test equipment and data analysis. Developed firmware and software applications using Quartus and Eclipse tools. Worked with customer throughout initial architecture specification, hardware and software development and continuing into the production phase. Other project work, board design, and firmware/software development with Cypress PSoC V microcontroller with CAN bus communications for antenna applications. Wrote test plans and perform design reviews. Performed testing against customer specifications and reliability qualification testing. Worked with manufacturing for board and system production and verification testing prior to customer delivery. Recognized with Special Achievement award for work on beam steering project. Active Top Secret security clearance. From December 2010 to December 2015 (5 years 1 month) FPGA & ASIC Design Engineer @ Developed the first integrated 10Gb/s Optical and Electrical Systems Tester which allows for performance and conformance testing of 10 Gb/s devices and systems to IEEE 802.3ae and ITU SONET standards. This provided a portable, faster, and more cost effective means of performing the standards testing. Designed FPGA code for 10Gb/s Data Pattern Source and Receiver for SONET framed and unframed data and 10GbE packet data. Collected BER statistics on RX data as well as bit and protocol testing (PPP handshake). Data rates ranging from 9.95 Gbps to 11.7 Gbps were also achieved.
FPGA control with PCI bus 32 bit/33 MHz interface via software.
Interfaced with Khatanga 10GbE/POS OC192c Framer and Hudson OC-192 Digital Wrapper device for OTN data rates. Used Multiple FPGAs to allow for bypassing SONET Framer ASIC to send and receive unframed data patterns (PRBS)
Designed Control logic for analog and digital devices in FPGA (transponders, attenuators, optical switches, ADC, DACs, potentiometers, temperature sensors, Voltage/Power monitors, Broadcom Mux/Demux chip, Gennum CDRs). I2C and SPI protocols used to control various devices. Used PLLs to provide a quality clock source to the FPGAs and ASICs.
Performed system testing on prototypes and production systems, including verification of data patterns and protocols using Anritsu and IXIA testers for SONET framed and unframed data and 10GbE protocol checking. Used logic analyzers, oscilloscopes and DVMs for board debug. Experienced with Xilinx Virtex-E, Virtex-II, Virtex-II Pro, Spartan3 and Virtex-4 FPGAs and Xilinx ISE software for place & route. Implemented synthesis of VHDL code with Synplify Pro and Leonardo Spectrum. Used Modelsim for simulation and Xilinx Chipscope Pro software for FPGA debug.
Reviewed ORCAD schematics for various boards developed, including high speed FPGA Board and physical layer optics board.
Developed control algorithms and scripts for software group to control system and FPGA functionality. From January 2001 to August 2009 (8 years 8 months) Hardware Engineer @ Worked on design of SNOWFLAKE ASIC, which provides connectivity between multiple Queue Manager subsystems. Include Receive and Transmit FIFOs and Scheduling logic to control the flow of data. These QMS subsystems are part of the latest generation of wire speed Layer 7 switch products. ASIC was designed in 0.25 micron, 1.5V CMOS technology using the Toshiba library. Worked on RTL and gate level full chip simulations using Modelsim and ran gate level simulations using NCVerilog. SDF timing was included in the gate level simulations. Generated test vectors using the Toshiba toolkit, including RAM BIST and NAND tree testing. Developed pinout, power/ground and SSO calculations for the ASIC. Developed full chip synthesis scripts for an initial version of the ASIC using SYNOPSYS. From November 1999 to December 2000 (1 year 2 months) Senior ASIC Design Engineer @ Worked on design of 10/100/GigaBit Ethernet Media Access Control ASICs for workgroup switches. The Tsunami ASIC, which is currently in production, is a MAC and Switch chip combined on one ASIC. Design used VHDL and Verilog HDL code, development of testbenches for full system simulation (including MAC, Switch chip, PHYs, etc.). ModelTech simulator used for design verification on SUN workstations on RTL code, gate level simulations and with SDF. Developed SYNOPSYS scripts for synthesis of HDL code at 75 MHz with multiple clock sources. Used SYNOPSYS PrimeTime for static timing analysis on rtl and with SDF files. Performed scan and jtag insertion using SYNOPSYS Test Compiler.
Worked with NEC OpenCAD and LSI logic design tool kits for development of ASICs. This included design rule checking, generation of test vectors, creation of technology library models for simulation and synthesis, pin/pad assignment, etc. From March 1998 to November 1999 (1 year 9 months) Member of Technical Staff @ Worked on design of high performance PRML Read Channel ICs used in disk drives. Designed a first generation Servo Digital Signal Processor using Verilog HDL code, SYNOPSYS and 0.35 micron CMOS technology. Performed full chip simulation, static timing analysis, and debug of parts in the lab using evaluation boards. Used back annotation of layout capacitance for accurate timing analysis and simulation. Worked with test engineers on generation of manufacturing screening tests and first silicon debug. The ASIC was mixed signal, including digital and analog components. Interfaced with A-to-D converter, VCO, AGC, and PLLs.
Designed Sequence Detector using signals equalized to EPR4. Includes lookup table, 10-state ACS units, and Path memory. Used schematic capture, a transistor level simulator and an architectural level C program to generate vectors for simulation.
Modified the design of an Encoder/Decoder circuit used to read/write data to a Magnetic disk drive for next generation read channel. Design goals of 320 MHz were achieved. From January 1996 to February 1998 (2 years 2 months) Senior Design Engineer @ Worked on ORION, the design for the next generation high-end UNISYS A-Series computer. This entails conceptual design of the stack architecture, VLSI gate array development using VHDL, SYNOPSYS design tools, and XVISION on UNIX based HP workstations. Includes design of a hardware prototype using a hardware simulation language, testing of this prototype, delay analysis, CAD implementation and simulation of the array using ECL and CMOS logic gates.
Designed and developed the Central Processor for the A19 large scale, high performance computer. In October 1991, when the A19 was publicly announced, it was the fastest computer in the world. Received an Outstanding Achievement Award for my work on the A19. From July 1986 to December 1995 (9 years 6 months)
MSEE, Computer Engineering @ Villanova University From 1991 to 1995 BSEE, Electrical/Computer Engineering @ Drexel University From 1981 to 1986 Fox Chase Elementary Todd Watts is skilled in: ASIC, FPGA, Verilog, VHDL, RTL design, PWB design, Static Timing Analysis, Integrated Circuit Design, ModelSim, Manufacturing, Simulations, Hardware Architecture, PCB design, Debugging, Electronics
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