Tam Cao
Senior Principal Engineer - FPGA Design Verification at BAE Systems, Inc. | Houston, Texas, United States
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Tam Cao serves as a Senior Principal Engineer specializing in FPGA Design Verification at BAE Systems, Inc., where he is recognized for his results-oriented approach and reliability in delivering high-quality engineering solutions. With a robust background in semiconductor technology and embedded systems, Tam plays a pivotal role in ensuring the integrity and functionality of complex System on Chip (SoC) designs. His expertise spans a variety of critical areas, including SystemVerilog, formal verification methodologies, and advanced debugging techniques.
At BAE Systems, Tam is currently leading key projects that focus on the verification of FPGA designs, utilizing tools such as Formality and Gatesim with SDF annotation to ensure compliance with stringent industry standards. His proficiency in scripting languages like Tcl, Perl, and Shell scripting allows him to automate verification processes, enhancing efficiency and accuracy in testing. Tam's commitment to excellence is evident in his ability to translate complex technical requirements into actionable verification strategies that yield tangible results.
In addition to his technical acumen, Tam is known for his collaborative spirit, often working closely with cross-functional teams to drive innovation and problem-solving. His contributions not only help in mitigating risks associated with design flaws but also play a crucial role in the successful deployment of cutting-edge technologies within the defense sector. As a reliable engineer, Tam continues to make significant strides in advancing FPGA design verification, ensuring that the solutions developed at BAE Systems are not only effective but also impactful in real-world applications.
Senior Principal Engineer - FPGA Design Verification at BAE Systems, Inc. in August 2023 to Present
FPGA Verification Engineer at Ciena in October 2020 to June 2023
Verification Engineer (Contract) at Ambiq in June 2020 to September 2020
Sr. Staff ASIC Engineer (Lead Verification) at Seagate Technology in March 2008 to June 2020
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Universal Verification Methodology (UVM)
SystemVerilog, Specman, SystemC, C/C++
VMM, RMM, eRM, minimal exposure to UVM
Tcl, Perl, Shell scripting
Formality, Gatesim (with SDF annotation)
Firmware
SystemVerilog
Testing
Debugging
SCSI
ASIC
SATA
Semiconductors
ARM
FPGA
SoC
Verilog
Embedded Systems
Perl
Functional Verification
IC
Application-Specific Integrated Circuits (ASIC)
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Discover more about BAE Systems, Inc.What is Tam Cao email address?
Email Tam Cao at [email protected]. This email is the most updated Tam Cao email found in 2026.
How to contact Tam Cao?
To contact Tam Cao send an email to [email protected]. (updated on November 04, 2024)
What company does Tam Cao work for?
Tam Cao works for BAE Systems, Inc.
What is Tam Cao's role at BAE Systems, Inc.?
Tam Cao is Senior Principal Engineer - FPGA Design Verification
What is Tam Cao's Phone Number?
Tam Cao's phone (214) ***-*302
What industry does Tam Cao work in?
Tam Cao works in the Defense And Space Manufacturing industry.
Tam Cao Email Addresses
Tam Cao Phone Numbers
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