Sharan Nagesh
PDG- Peripheral Connectivity Hub Circuit Design Engineer Intern
Intern at Intel, actively looking for Entry Level opportunities starting from December 2015 in IC Design/validation
Santa Clara, California
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Sharan Nagesh's Email Addresses & Phone Numbers
About Sharan Nagesh
•Academic experience in ASIC design flow, FPGA and microprocessor design •Industry level experience in RTL design and validation, System Verilog, OVM and assertion methodology •Good understanding of industry standard interfaces, bus functional model and Verilog simulator tools •Experience in memory design (SRAM), full custom and semi-custom layout design •Good understanding of Computer architecture, Static timing analysis and...
•Academic experience in ASIC design flow, FPGA and microprocessor design •Industry level experience in RTL design and validation, System Verilog, OVM and assertion methodology •Good understanding of industry standard interfaces, bus functional model and Verilog simulator tools •Experience in memory design (SRAM), full custom and semi-custom layout design •Good understanding of Computer architecture, Static timing analysis and experience in using Primetime •Skilled in Verilog, System Verilog, C , C++ and Perl • Adept in using EDA tools Cadence: Cadence Virtuoso, Cadence ICFB, NC-Verilog, EDI-Encounter Synopsys: IC-Complier, Design vision, Library Compiler, Waveview, Liberty NCX • Adept in using simulation tools like Xilinx ISE, ModelSim, Hspice • Hardware experience : Nexys™3 Spartan-6 FPGA Board, Texas Instruments MSP430 Microcontroller ,Stellaris Arm Cortex-M3 EVALBOT, Stellaris Arm Cortex-M4 Specialities: CMOS VLSI Circuit design, Cadence IC design and layout tools, RTL design (Verilog, System Verilog &VHDL), RTL Validation using OVM, FPGA design and Team playingPDG- Peripheral Connectivity Hub Circuit Design Engineer Intern @ •Responsibilities include RTL Design and validation of Intel’s next generation SOC, Full Chip integration & architectural validation. •Designed AHB Master for the existing 3 Slaves and established AHB Bus transactions between master and the slaves. •Developing the tests specific to connectivity using system Verilog, in OVM environment on LINUX platform. •Verifying the design by running simulation waveforms on RTL, post synthesis (GLS) and post layout Netlists. •Performing ECOs on the post synthesis and post layout Netlists to meet the deadlines •Understanding of industry standard JTAG interface for on chip debugging purpose, bus functional model, OVM and assertion methodology. Familiar with industry standard tools for Verilog compilation and simulation. From January 2015 to November 2015 (11 months) Master's degree, Electrical and Electronics Engineering / Digital systems @ The University of Texas at Dallas From 2013 to 2015 Bachelor of Engineering (B.E.), Electronics and Communications Engineering @ Bangalore Institute Of Technology From 2009 to 2013 Sharan Nagesh is skilled in: Verilog, VLSI, ModelSim, Cadence Virtuoso, ASIC, SPICE, Microsoft Office, Xilinx, C++, Synopsys tools, C, VHDL, Integrated Circuit Design, FPGA, Cadence
Sharan Nagesh’s Personal Email Address, Business Email, and Phone Number
are curated by ContactOut on this page.About Sharan Nagesh's Current Company
Intel Corporation•Responsibilities include RTL Design and validation of Intel’s next generation SOC, Full Chip integration & architectural validation. •Designed AHB Master for the existing 3 Slaves and established AHB Bus transactions between master and the slaves. •Developing the tests specific to connectivity using system Verilog, in OVM environment on LINUX platform. •Verifying the design by running simulation waveforms... •Responsibilities include RTL Design and validation of Intel’s next generation SOC, Full Chip integration & architectural validation. •Designed AHB Master for the existing 3 Slaves and established AHB Bus transactions between master and the slaves. •Developing the tests specific to connectivity using system Verilog, in OVM environment on LINUX platform. •Verifying the design by running simulation waveforms on RTL, post synthesis (GLS) and post layout Netlists. •Performing ECOs on the post synthesis and post layout Netlists to meet the deadlines •Understanding of industry standard JTAG interface for on chip debugging purpose, bus functional model, OVM and assertion methodology. Familiar with industry standard tools for Verilog compilation and simulation.
Frequently Asked Questions about Sharan Nagesh
What company does Sharan Nagesh work for?
Sharan Nagesh works for Intel Corporation
What is Sharan Nagesh's role at Intel Corporation?
Sharan Nagesh is PDG- Peripheral Connectivity Hub Circuit Design Engineer Intern
What is Sharan Nagesh's personal email address?
Sharan Nagesh's personal email address is s****[email protected]
What is Sharan Nagesh's business email address?
Sharan Nagesh's business email addresses are not available
What is Sharan Nagesh's Phone Number?
Sharan Nagesh's phone (213) ***-*236
What industry does Sharan Nagesh work in?
Sharan Nagesh works in the Semiconductors industry.
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