May W
Principal Physical Design Engineer at WD Corp | Campbell, California, United States
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May W. is a Principal Physical Design Engineer at WD Corp, where she leverages over eight years of hands-on experience in ASIC and SoC design to drive innovative solutions in advanced semiconductor technologies. Her expertise spans the entire RTL/netlist to GDS2 flow, encompassing critical phases such as synthesis, floor planning, place and route (P&R), clock tree synthesis (CTS), and static timing analysis (STA). May’s meticulous approach to physical design has led to significant achievements, including a remarkable 20% reduction in power consumption through the application of low-power techniques and a 6% decrease in block area after optimizing P&R processes.
At WD Corp, May is currently spearheading several key projects focused on enhancing the efficiency and performance of complex integrated circuits. She excels in executing and debugging essential design checks, including DRC, LVS, ERC, and DFM, ensuring that all designs meet stringent industry standards. Her proficiency in signal integrity analysis, including electromagnetic (EM) effects, crosstalk, and IR drop analysis, positions her as a vital asset in maintaining the reliability of high-performance designs.
May's skill set is further complemented by her expertise in die size planning, IO and block placement, and DFT scan chain reordering, making her a well-rounded engineer capable of tackling the multifaceted challenges of modern semiconductor design. With a strong foundation in EDA tools like Innovus and a deep understanding of VHDL, May W. continues to push the boundaries of physical design, contributing to WD Corp's reputation as a leader in the semiconductor industry. Her passion for innovation and commitment to excellence ensure that she remains at the forefront of technological advancements in the field.
Principal Physical Design Engineer at WD Corp in January 2014 to Present
Staff Physical Design Engineer at Broadcom Inc. in January 2011 to January 2014
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multiple power domain Electromigration EM/IR
IO and block placement
die size planning
layout integration
2.5D 3D IC
Floorplanning
Physical Design
Static Timing Analysis
TCL
Programming
Application-Specific Integrated Circuits (ASIC)
Very-Large-Scale Integration (VLSI)
Semiconductors
System on a Chip (SoC)
Debugging
Integrated Circuits (IC)
Perl
Verilog
Place & Route
Clock Tree Synthesis
Timing Closure
Physical Verification
Logic Synthesis
DFT
EDA
Power Analysis
Signal Integrity
Formal Verification
ICC
ICC2
Innovus
Primetime
Timing
Cadence Virtuoso
CMOS
Microsoft Office
ciruit design
VHDL
Cadence Spectre
Circuit Design
HTML
tech-savvy
Synopsys tools
Tapeout
scripting
Low-power Design
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What is May W email address?
Email May W at [email protected]. This email is the most updated May W email found in 2026.
How to contact May W?
To contact May W send an email to [email protected]. (updated on October 29, 2024)
What company does May W work for?
May W works for WD Corp
What is May W's role at WD Corp?
May W is Principal Physical Design Engineer
What is May W's Phone Number?
May W's phone (213) ***-*199
What industry does May W work in?
May W works in the Software Development industry.
May W Email Addresses
May W Phone Numbers
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