Jon Cooper
Custom IC Methodology Solutions Director – Physical Design at Cadence Design Systems | Mount Airy, Maryland, United States
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Jon Cooper serves as the Custom IC Methodology Solutions Director for Physical Design at Cadence Design Systems, where he plays a pivotal role in advancing the capabilities of custom and analog IC physical design for enterprise customers utilizing cutting-edge FinFET technologies, including 7nm, 5nm, and 3nm processes. With a strong focus on enhancing design efficiency, Jon leads the CIC Methodology Implementation Group's Physical Design team, ensuring that clients can navigate the complexities of advanced node designs seamlessly.
In his current role, Jon is instrumental in driving enhancements to Electronic Design Automation (EDA) tools, tailoring solutions that address the unique challenges faced by engineers in the semiconductor industry. His expertise in mixed-signal design and physical implementation methodology allows him to develop customized workflows that optimize mixed-signal floorplanning and interoperability, ensuring that designs meet stringent performance and power requirements.
Jon is also dedicated to knowledge transfer within the organization, developing and delivering targeted training programs that empower Cadence employees and clients alike. His proficiency in scripting languages such as TCL and PERL, combined with his experience in timing model generation, enables him to create robust solutions that streamline the design process. By fostering collaboration and innovation, Jon Cooper is not only enhancing the capabilities of Cadence’s EDA tools but also setting new standards for efficiency and effectiveness in custom IC physical design.
Custom IC Methodology Solutions Director – Physical Design at Cadence Design Systems in September 2020 to Present
Sr Principal Application Engineer at Cadence Design Systems in May 2016 to September 2022
Staff Methodology Services Engineer at Cadence Design Systems in May 2012 to September 2022
Principal Applications Engineer, AMS Methodology Services at Cadence Design Systems in May 2002 to May 2012
Engineering Group Leader - FPGA at ATMEL in June 1991 to May 2002
Intern at Johns Hopkins University Applied Physics Laboratory in June 1988 to December 1988
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Mixed Signal
EDA
Semiconductors
FPGA
ASIC
Mixed-Signal Floorplanning
Mixed-Signal Physical Implementation Methodology
Mixed-Signal Interoperability
Scripting - SKILL, TCL, PERL
Timing Model Generation
Static Timing Analysis
Timing-Driven Digital Physical Implementation
IC
Microelectronics
CMOS
TCL
Analog
SoC
VLSI
Integrated Circuit Design
Physical Design
Verilog
Physical Verification
Analog Circuit Design
LVS
System on a Chip (SoC)
Field-Programmable Gate Arrays (FPGA)
Very-Large-Scale Integration (VLSI)
Application-Specific Integrated Circuits (ASIC)
Integrated Circuits (IC)
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Discover more about Cadence Design SystemsWhat is Jon Cooper email address?
Email Jon Cooper at [email protected]. This email is the most updated Jon Cooper email found in 2026.
How to contact Jon Cooper?
To contact Jon Cooper send an email to [email protected].
What company does Jon Cooper work for?
Jon Cooper works for Cadence Design Systems
What is Jon Cooper's role at Cadence Design Systems?
Jon Cooper is Custom IC Methodology Solutions Director – Physical Design
What is Jon Cooper's Phone Number?
Jon Cooper's phone (301) ***-*234
What industry does Jon Cooper work in?
Jon Cooper works in the Software Development industry.
Jon Cooper Email Addresses
Jon Cooper Phone Numbers
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