Jiang Liu
Tech Lead, Principle R&D NVM Test and Logic Design Engineer at NXP Semiconductors | Austin, Texas, United States
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Jiang Liu is a seasoned Tech Lead and Principal R&D NVM Test and Logic Design Engineer at NXP Semiconductors, where he plays a pivotal role in advancing the company's Non-Volatile Memory (NVM) technologies. With over 16 years of experience in the semiconductor industry, Jiang has honed his expertise in leading cross-functional teams through complex New Technology and Product Introductions (NTI/NPI). His current responsibilities involve spearheading multiple post-silicon R&D project teams focused on integrating innovative NVM technologies, including proprietary flash technologies like 90nm TFS and 40nm 2T, as well as cutting-edge solutions such as Resistive RAM (RRAM) and ESF3 from major foundries.
Jiang's deep knowledge in ATE test development and RTL design/verification has been instrumental in driving successful outcomes for NXP’s product lines. His technical decision-making skills are complemented by a results-oriented approach that emphasizes workflow improvement and team collaboration. Jiang's leadership not only fosters a culture of innovation but also ensures that projects are delivered on time and meet the highest quality standards. His proficiency in embedded systems, mixed-signal design, and application-specific integrated circuits (ASIC) further enhances his capability to navigate the complexities of modern semiconductor development.
As a thought leader in the field, Jiang is committed to pushing the boundaries of NVM technology, contributing to NXP's reputation as a leader in the semiconductor space. His passion for technology and continuous improvement drives him to explore new methodologies and tools, ensuring that NXP remains at the forefront of the industry.
Tech Lead, Principle R&D NVM Test and Logic Design Engineer at NXP Semiconductors in March 2018 to Present
Senior Principal SoC Product Engineer (Technical lead) at NXP Semiconductors in June 2022 to Present
Tech lead, Senior Principal NVM R&D Test and Logic Design Engineer at NXP Semiconductors in March 2022 to August 2024
Senior NVM R&D Test and Logic Design Engineer at NXP Semiconductors in February 2014 to March 2018
SoC Test Engineer at NXP acquires Freescale Semiconductor in December 2011 to February 2014
SoC System Engineering at NXP acquires Freescale Semiconductor in August 2011 to December 2011
SoC Burn in Test Engineer at NXP acquires Freescale Semiconductor in October 2009 to July 2011
SoC Product Engineer at NXP acquires Freescale Semiconductor in June 2008 to October 2009
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C++
Microcontrollers
Embedded Systems
Validation
Debugging
PowerPC
Embedded C
C
Electronics
Mixed Signal
SoC
Analog
Microelectronics
Application-Specific Integrated Circuits (ASIC)
Semiconductors
Testing
System on a Chip (SoC)
Verilog
Ruby
Linux
Leadership
Communications
Cross-functional Team Leadership
RTL Design
RTL
Verification and Validation (V&V)
Cross-team Collaboration
Digital IC Design
Flash Design
RRAM
Design
Jira
Confluence
Bitbucket
Atlassian Bamboo
GitHub
ATE
Agile Methodologies
Flash
NVM
C (Programming Language)
Firmware
NPI Management
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Discover more about NXP SemiconductorsWhat is Jiang Liu email address?
Email Jiang Liu at [email protected] and [email protected]. This email is the most updated Jiang Liu email found in 2026.
What is Jiang Liu phone number?
Jiang Liu phone number is +18659747138.
How to contact Jiang Liu?
To contact Jiang Liu send an email to [email protected] or [email protected]. If you want to call Jiang Liu try calling on +18659747138.
What company does Jiang Liu work for?
Jiang Liu works for NXP Semiconductors
What is Jiang Liu's role at NXP Semiconductors?
Jiang Liu is Tech Lead, Principle R&D NVM Test and Logic Design Engineer
What industry does Jiang Liu work in?
Jiang Liu works in the Semiconductor Manufacturing industry.
Jiang Liu Email Addresses
Jiang Liu Phone Numbers
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