I am Gaurav Saini and have 8 years of experience in Physical design and Static Timing Analysis. Along with PD and STA, I have also worked on Synthesis, Constraints Generation & validation activities. I have done 3 tapeouts on 28 nm and multiple tapeouts on 45 nm, 65nm and 90 nm technologies. I have worked with different
I am Gaurav Saini and have 8 years of experience in Physical design and Static Timing Analysis. Along with PD and STA, I have also worked on Synthesis, Constraints Generation & validation activities. I have done 3 tapeouts on 28 nm and multiple tapeouts on 45 nm, 65nm and 90 nm technologies. I have worked with different clients – US, Japan and interacted with teams available at different time zones. I have been to US (Fremont, CA) for 6 weeks for the kickstart of a project.
I have valid H1B till august 2017.
I can explore my ability with following skills and tools.
Encounter (Cadence) – Block level and top level design implementation
ICCompiler (Synopsys) - Block level implementation
Olympus-SoC (Mentor) – For hierarchical flows, and Correlation activities with PT.
Static Timing Analysis: Prime Time/SI
Synthesis: Design Compiler
RC Extraction: Star RCXT
Physical Verification: Calibre DRC/LVS
Formal Verification: Formality (Synopsys)
Scripting Languages: TCL, perl, shell
Status Reporting: Pinpoint
Other tools: Spyglass-TxV, Conformal-LEC, GCA
Application Packages MS-office (Word, Power Point, Excel)
Technical Lead @ Working on block level designs of customer networking chip on 16nm and 28 nm for the complete netlist to GDSII activities using Encounter for place and route, IC validator for Physical verification, PrimeTime-SI for timing Signoff. From November 2014 to Present (1 year 2 months) PnR Product Engineer II @ I was mainly responsible for all timing engine related activities for Olympus-SoC Place n Route tool. Also responsible for hierarchical flows like Partition SDC ( PSDC) reference flow generation, HTP-ILM reference flow development, Distributed STA flow, etc. From June 2012 to September 2014 (2 years 4 months) Sr. Design Engineer @ I was responsible for Place n Route ( netlist to GDSII) of top level and block level designs of ST testchips for memory and standard cell characterization and testing. From July 2010 to May 2012 (1 year 11 months) Noida Area, IndiaOnsite Design Engineer at ST Microelectronics @ Exception ( False path and Multi-cycle path ) generation and validation. Performing Spyglass checks for RTL and constraints. From April 2010 to June 2010 (3 months) Noida Area, IndiaPhysical Design Engineer @ Performing Placement Optimization, Clock Tree Synthesis, Post Route Optimization, Sign-off with PT with CCS libraries, Synthesis and Static timing Analysis, Formal Verification at every stage. From July 2007 to April 2010 (2 years 10 months) Noida Area, India
B.Tech, Electronics and Instrumentation Control @ Maharshi Dayanand University From 2003 to 2007 Gaurav Saini is skilled in: Static Timing Analysis, ASIC, Floorplanning, Physical Design, Place & Route, Logic Synthesis, Synopsys Primetime, VLSI, Clock Tree Synthesis, Compilers, Formal Verification, VHDL, SoC, Microelectronics, Verilog, Perl, TCL, RTL Design
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