Chee Ng
Sr Principal Application Engineer at Cadence | Santa Barbara-Santa Maria Area
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Chee Ng serves as a Principal Application Engineer at Cadence Design Systems, where he leverages his extensive background in ASIC digital engineering to drive innovation in physical design methodologies. With a robust skill set that encompasses synthesis, auto-place-and-route (P&R), and static timing analysis (STA), Chee is instrumental in optimizing design performance, power, and area (PPA) for complex semiconductor projects. His expertise in low-power design synthesis, particularly in dynamic and glitch power optimization, positions him as a key contributor to projects focused on energy-efficient solutions in System on a Chip (SoC) designs.
At Cadence, Chee is actively involved in several high-impact projects, utilizing advanced tools such as Joules, Genus, Cerebrus, and Innovus to enhance digital design flows. His passion for developing and refining methodologies is evident in his work on RTL power scrubbing and reduction, where he applies his knowledge of Verilog and electrical rule checks to ensure robust and efficient designs. Chee’s experience in logic simulation, including Register File read/write operations, further complements his comprehensive approach to digital design and signoff.
In addition to his technical prowess, Chee is adept at utilizing scripting languages like Perl and tools like Microsoft Excel to streamline workflows and improve productivity. His commitment to continuous improvement and innovation in design processes not only elevates project outcomes but also contributes to the broader goals of the semiconductor industry, making him a valuable asset to Cadence Design Systems and its clients.
Sr Principal Application Engineer at Cadence in July 2024 to Present
Principal Application Engineer at Cadence in May 2022 to February 2025
Principal Staff Digital IC Design Engineer at Motorola Solutions in August 2021 to May 2022
Staff Digital IC Design Engineer at Motorola Solutions in January 2017 to January 2021
Senior SOC Design Engineer at Intel Corporation in August 2010 to September 2016
IC Design Engineer at Intel Corporation in June 2007 to August 2010
Industrial Trainee at Intel Corporation in May 2006 to July 2006
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Verilog
Static Timing Analysis
ASIC
Primetime
TCL
Circuit Design
FPGA
Functional Verification
Logic Design
Perl
Integrated Circuit Design
Place & Route
SoC
Semiconductors
JavaScript
HTML5
css
ICC
SRAM
Electrical Rule Check
Microsoft Excel
Clock Tree Synthesis
Characterization
Variation Analysis
Simulations
ECO flow
Noise Reduction
Low-power Design
System on a Chip (SoC)
Field-Programmable Gate Arrays (FPGA)
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Discover more about CadenceWhat is Chee Ng email address?
Email Chee Ng at [email protected]. This email is the most updated Chee Ng email found in 2026.
How to contact Chee Ng?
To contact Chee Ng send an email to [email protected].
What company does Chee Ng work for?
Chee Ng works for Cadence
What is Chee Ng's role at Cadence?
Chee Ng is Sr Principal Application Engineer
What is Chee Ng's Phone Number?
Chee Ng's phone (**) *** *** 757
What industry does Chee Ng work in?
Chee Ng works in the Software Development industry.
Chee Ng Email Addresses
Chee Ng Phone Numbers
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