A versatile electronic engineer with a wide range of experience in hardware, FPGA RTL and software design. Developed designs for video processing, telecommunications and high performance computing applications. An excellent team member with a flexible approach to development, with experience in leading and managing teams. Specialities: Platform architecture, requirements definition and analysis, high-level and detailed specification, complex
A versatile electronic engineer with a wide range of experience in hardware, FPGA RTL and software design. Developed designs for video processing, telecommunications and high performance computing applications. An excellent team member with a flexible approach to development, with experience in leading and managing teams. Specialities: Platform architecture, requirements definition and analysis, high-level and detailed specification, complex and high speed board design, FPGA RTL, design debugging and verification. Hardware design: Board designs for CPUs, DSPs, FPGAs and SOCs. Analogue and digital circuitry. High speed buses including: DDR3, QDR memory interfaces. Multi gigabit transceiver links. Power supplies. Dense multi-layer PCB designs. DFA + DFT. RTL design: VHDL, Verilog, System Verilog. Designs for data and control paths for video and telecom applications. Designs for Altera, Xilinx and Lattice devices. Programming languages: Python, C, C++, BASH scripting.
Developed hardware and FPGA designs for Video Production Switchers. Board design work included: analogue and SDI video IO, embedded CPUs and FPGAs, DDR2/3 memory and PCIe interfaces, PLLs and low jitter clock networks. RTL designs for video processing modules for SD/HD/3G video formats. Captured design requirements, developed system architectures, conducted feasibility studies and technical investigations. Optimised designs to meet cost, performance and feature set requirements. Worked with 3rd party contractors in technical and oversight roles. From September 2007 to Present (7 years 9 months) Ottawa, Canada Created designs for a network Content Screening Gateway (CSG). Developed VHDL code for hardware acceleration units and a processing engines in the system. Wrote a software compiler in Python, plus debug utilities for processing engines. Created regression tests for FPGA designs. Created BASH and Python scripts for debugging in lab and verification environments. Conducted peer code reviews. Developed FPGA design constraints. Involved with hardware debug for various circuit and PCB designs for the CSG. From April 2006 to July 2007 (1 year 4 months) Amersham, Buckinghamshire, UK Responsible for specification, implementation and test of embedded CPU, FPGA and DSP platforms for many different applications and markets. Design work included: baseband analogue and digital circuitry, PCB, VHDL for CPLDs and FPGAs, plus software development. Contributed to client and subcontractor discussions, feasibility studies, design reviews, environmental testing, manufacturing stages and mechanical design. From September 2001 to April 2006 (4 years 8 months) Great Chesterford, Essex, UK
Master of Engineering (MEng) Hons., Electronic Engineering (Computing) @ The University of Sheffield From 1997 to 2001 CHRIS MAY is skilled in: FPGA, Hardware Architecture, Embedded Systems, PCB design, VHDL, Xilinx, Verilog, Electronics, Debugging, FPGA design, High Speed Digital, Testing, Hardware, Digital Signal..., System Architecture, Processors, Altera, Schematic Capture, Embedded Software, Microcontrollers, Analog, Circuit Design, Software Development, C++, Software Design, SystemVerilog, Design for Manufacturing, Firmware, Orcad, Telecommunications, Team Leadership, Hyperlynx, LTSpice, Environmental Testing, RTL Design, CPLD, PCIe, Python, Power Supplies, Analog Circuit Design, Device Drivers, Digital Electronics, RTOS, DDR2, SoC
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