Chandu VaghasiaSr. Staff Component Design Engineer/DV Lead
San Jose, California
Sr. Staff Component Design Engineer/DV Lead
R&D Verification Technical Lead
Sr. R&D Verification Engineer
ASIC Design Verification Consultant
ASIC Verification Consultant
Member, Technical Staff
ASIC Verification Consultant
ASIC Verification Consultant
ASIC Verification Engineer
ASIC Verification Consultant
International Technological University
Dharmsinh Desai Institute of Technology
A.V.P.T.I.
VMM Goladhar
Recommendations: 10
- Languages: Verilog, System Verilog, Vera, C/C++
- Methodologies: OVM,VMM,RVM
-USB, XHCI, PCIE, SAS, SATA, AXI, AHB, APB, Networking, Multimedia
- Scripting Languages :: Perl, Shell
- WaveformViewer::Dve,Nwave,Simvision
- Repository Tools :: CVS, Perforce, SVN
- Bug tracking :: Mantis, CRM
SystemVerilog