Latha PadavalaDesign Verification Consultant
Plano, Texas
Design Verification Consultant
Digital ASIC Design Engineer
Sr.Digital Design Engineer
Digital Design Consultant
Sr. Digital Design Engineer
System IP Design/Verification Staff Engineer
Mixed Signal Design Verification Engineer
Design engineer
Component design Engineer
Arizona State University
Jawaharlal Nehru Technological University
Recommendations: 7
Verilog
ModelSim
VHDL
NCSim
Synopsys tools
Xilinx ISE
Matlab
Simulink