Top Staff Design Engineers in Greater San Diego Area
Judy Alvarez-Gallardo
Lead ASIC Design Engineer
Greater San Diego Area
Lead ASIC Design Engineer
Staff Design Engineer
Senior Design Engineer
Senior Design Engineer
R&D Hardware Engineer
University of California San Diego
University of California San Diego
Recommendations: 4
Static Timing Analysis
Logic Synthesis
Verilog
j****[email protected]
Ashutosh Rane
Staff Design Engineer
Greater San Diego Area
Staff Design Engineer
Sr. Staff Engineer
Hardware Engineer, Level 3
Sr. Product Engineer
Product Development Engineer
Intern
California State University-Sacramento
University of Mumbai
Recommendations: 0
Debugging
ASIC
DFT
Verilog
Wireless
Embedded Systems
Hardware Architecture
ARM
a****[email protected]
Yu Huang
Staff Design Engineer
Greater San Diego Area
Staff Design Engineer
Staff Design Engineer
Sr. staff design engineer
Design Engineer
Engineer
University of Utah
Northwest Polytechnic Univ
Northwest Polytechnic Univ., Xi'an, P.R.China
Recommendations: 0
Mixed Signal
Temperature Sensors
LDO
Comparators
Bandgap References
Dividers
IO Design
IBIS
t****[email protected]
Abdul Mohammed
Senior Staff Engineer/SoC PD Lead
Greater San Diego Area
Senior Staff Engineer/SoC PD Lead
Senior Physical Design Engineer
Staff Design Engineer
ASIC Physical Design Engineer
Lead Physical Design Engineer(Consultant)
Osmania University
Recommendations: 0
a****[email protected]
Michael Paquette
Staff Engineer (Modem HW)
Greater San Diego Area
Staff Engineer (Modem HW)
Senior Staff Engineer
Staff Engineer/Manager
Staff Design Engineer
Senior Engineer
Design Engineer
University of California, San Diego
Recommendations: 0
Verilog
SystemVerilog
RTL design
WiMAX
SoC
Wireless
RTL verification
Mixed Signal
m****[email protected]
k****[email protected]
Antonio Geremia
Principal Systems Engineer
Greater San Diego Area
Principal Systems Engineer
Principal ASIC Design Engineer
Senior Staff Design Engineer
Staff Design Engineer
Staff Design Engineer
engineer
University of San Diego
Recommendations: 0
Static Timing Analysis
Verilog
Semiconductors
Mixed Signal
SoC
SystemVerilog
ASIC
Logic Synthesis
j****[email protected]
j****[email protected]
Manish Dangol
Senior Design Engineer
Greater San Diego Area
Senior Design Engineer
Digital ASIC Design Engineer
Staff Design Engineer
Electronic Design Intern
Senior Staff Design Engineer
Graduate Teaching Assistant
North Dakota State University
Maulana Azad National Institute of Technology
Recommendations: 0
ASIC
RTL design
Verilog
Static Timing Analysis
Integrated Circuit...
SystemVerilog
VHDL
C
m****[email protected]
d****[email protected]
Kristian Madsen
Undergraduate Researcher
Greater San Diego Area
Undergraduate Researcher
Food Clerk
Principal Engineer
Intern
Staff Design Engineer
Intern
Graduate Researcher
Intern
Intern
Graduate Researcher
RFIC Design Engineer
Senior Engineer
University of California, San Diego
University of California, San Diego
Santa Rosa Junior College
Recommendations: 0
Electrical Engineering
RF
Mixed Signal
Matlab
Engineering
IC
Labview
Solidworks
k****[email protected]
Jerry Alcorn
Senior Digital Engineer
Greater San Diego Area
Senior Digital Engineer
Associate Member, Technical Staff
ASIC Design Engineer
Senior FPGA Engineer
Staff Engineer, Digital Design
Staff Design Engineer
Digital Design Engineer 4
California State University-Sacramento
Recommendations: 0
FPGA
ASIC
Integrated Circuit Design
Xilinx
Altera
Logic Synthesis
VHDL
Verilog
j****[email protected]
Bryan MBA
Design Verification Engineer
Greater San Diego Area
Design Verification Engineer
Co-owner and Board Member
Principal Design Engineer
Staff Digital Verification Engineer
Staff Digital Verification Engineer
Staff Design Engineer
Senior Design Engineer
Microprocessor Development Engineer
Test Development Engineer
University of California, San Diego - The Rady School of Management
Georgia Institute of Technology
Youngstown State University
Recommendations: 0
b****[email protected]
