Jay PatelSoftware Engineering Intern
Santa Clara, California
Software Engineering Intern
Partner Technology Manager (TPM/SWE and external partnerships)
MBA Graduate Student
Experienced Commercial Leadership Program (ECLP) Summer Associate
Senior ASIC Design Engineer
ASIC Design Engineer
Teaching Assistant - Electrical & Computer Engineering Dept.
Research Assistant - Electrical & Computer Engineering Dept.
Research Assistant - Materials Science Engineering Dept.
Carnegie Mellon University - Tepper School of Business
Carnegie Mellon University
Carnegie Mellon University
Recommendations: 0
ASIC
RTL design
Verilog
Computer Architecture
SoC
Static Timing Analysis
Logic Design
EDA