Top IC Design Engineers in San Jose, California
Ramsin Ziazadeh
Hardware Design Engineer
San Jose, California
Hardware Design Engineer
Principal Mixed-Signal IC Design Engineer
Oregon State University
Oregon State University
Recommendations: 4
PLL
IC
Mixed Signal
CMOS
Analog
Analog Circuit Design
Integrated Circuit...
Amplifiers
r****[email protected]
Namita Godara
summer intern
San Jose, California
summer intern
Electrical Engineer
Digital Design Engineer
Intern
Production & Test Engineering Intern
ASIC Design Engineer
Teaching Assistant
Student Grader
Santa Clara University
South Dakota State University
Jai Narain Vyas University
Recommendations: 3
Analog Circuit Design
Control System Design
VLSI
Low Voltage
High Voltage
Power Generation
Power Distribution
Switchgear
n****[email protected]
Till Kuendiger
Sr. ASIC/Layout Design Engineer
San Jose, California
Sr. ASIC/Layout Design Engineer
Platform Developer, co-op student
Test Engineer, co-op student
Development Student
DMA Design Engineer
Digital Architect, Intern
Senior Staff IC Design Engineer
Staff ASIC Design Engineer
Research Assistant
VLSI Systems Manager
Carleton University
University of Windsor
University of Windsor
Recommendations: 3
Verilog
Integrated Circuit...
SystemVerilog
CMOS
Functional Verification
RTL coding
Unix
VLSI
k****[email protected]
Abhishek Angadi
Modem Design Verification Lead
San Jose, California
Modem Design Verification Lead
Senior GPU Verification Engineer
Senior Modem Wireless Engineer
Staff I IC Design Engineer
Processor Verification Engineer
Software Engineer
Texas Tech University
S.D.M College of Engineering and Technology;
University of Pennsylvania - The Wharton School
Recommendations: 2
Verilog
Integrated Circuit Design
SystemVerilog
FPGA
ModelSim
SoC
C
Perl
a****[email protected]
Alan Ellis
Member Technical Staff
San Jose, California
Member Technical Staff
Principal Analog Design Engineer
Principal Analog/Mixed Signal/RF IC Design Engineer
Principal Analog/Mixed Signal IC Design Engineer
DMTS Analog IC Design Engineer
Staff Analog IC Design Engineer
Staff Test Development Engineer
Senior Test Development Engineer
Senior Product/Test Engineer
Test Development/Product Engineer
Santa Clara University
San Jose State University
Recommendations: 2
PLL
VCO
RFIC
Spectre
Amplifiers
Characterization
Analog
Mixed Signal
a****[email protected]
Hugo Lamarche
Senior IC Design Engineer - Configuration Group
San Jose, California
Senior IC Design Engineer - Configuration Group
Senior Staff Digital IC Design Engineer
Laboratory and Tutorial TA
Senior IC Design Engineer - SERDES Technology Group
Intern in Video Hardware
MTS RTL/Logic Design Engineer
University of Toronto
Polytechnique Montréal
Recommendations: 1
h****[email protected]
Shruthi Shivaswamy
Intern
San Jose, California
Intern
Sr ASIC Design Engineer
ASIC Design Engineer
Applications Engineer
Intern
Associate Software Engineer
Sr. DFT Engineer & Lead
Engineer Intern
SOC design engineer
Associate Entrepreneur in Residence
Syracuse University
Visvesvaraya Technological University
Recommendations: 1
VHDL
Verilog
C
Perl
Matlab
Scilab
s****[email protected]
Helene Chan
ASIC Design Engineer
San Jose, California
ASIC Design Engineer
Embedded Systems Engineer
Teaching Assistant
University of California, Santa Cruz
Recommendations: 0
ASIC
Embedded Systems
SoC
FPGA
Verilog
Logic Design
Debugging
Electrical Engineering
h****[email protected]
h*****@uniquify.com
Jayanth Srinivasa
Sr. Software Engineer
San Jose, California
Sr. Software Engineer
Technical Leader Engineering
Technical Leader Engineering
Sr. Software Engineer
Software Engineer
ASIC Design Engineer
Graduate Student Research Assistant
UC Berkeley School of Information
University of Michigan
Visvesvaraya Technological University
Recommendations: 0
Linux
Embedded Systems
Semiconductors
C++
C
ASIC
Perl
Verilog
t****[email protected]
Varun Agarwal
Summer Intern
San Jose, California
Summer Intern
AR/VR Engineer
Senior ASIC Design Engineer
Engineer
Senior Member Technical Staff
Staff ASIC Design Engineer
Cornell University
Indian Institute of Technology (Banaras Hindu University), Varanasi
Recommendations: 0
C
Perl
VHDL
C++
Simulations
Verilog
Shell Scripting
Computer Architecture
a****[email protected]
Hefei Zhu
ASIC Design Engineer Intern
San Jose, California
ASIC Design Engineer Intern
Senior ASIC Design Engineer
Senior Staff ASIC Design Engineer
Senior Staff ASIC Design Engineer
Senior Staff ASIC design Engineer
ASIC Design Engineer Intern
Fudan University
Zhejiang University
Recommendations: 0
ASIC
h****[email protected]
Andrew Tabalujan
Staff IC Design Engineer
San Jose, California
Staff IC Design Engineer
Staff Electrical Design Engineer
M.S. Research Assistant
Staff Serdes AMS Design Engineer
Oregon State University
Oregon State University
Recommendations: 0
Analog
Mixed Signal
Integrated Circuit Design
Simulations
RF
Characterization
SRAM
Spectre
a****[email protected]
Ajaychandar Chandrashekar
Volunteer Locomotive Engineer
San Jose, California
Volunteer Locomotive Engineer
Sr. Software Engineer
Software Engineer
IC Design Engineer
Member of Technical Staff
Technologist
Senior Software Engineer
University of Madras
San Jose State University
University of California, Berkeley, Haas School of Business
Recommendations: 0
TCL
BGP
TCP/IP
Software Quality Assurance
C
Unix/Linux
IXIA
Spirent Test Center
a****[email protected]
Venkateswarlu Muvva
Design Verification Lead
San Jose, California
Design Verification Lead
Senior Staff Design Verification Engineer
Senior Verification Consultant
ASIC Director
Senior ASIC Consultant
ASIC Verification Lead, Terayon Communications
Senior Verification Consultant
Senior ASIC Design Engineer
Acharya Nagarjuna University
Osmania University
UC Berkeley College of Engineering
Recommendations: 0
l****[email protected]
Gaurav Agrawal
Hardware Engineer
San Jose, California
Hardware Engineer
Sr ASIC Design Engineer
Hardware Engineer
IC Design Engineer
Hardware Engineer
VLSI Design Engineer
Technical Leader
Graduate Intern
Stanford University
The University of Texas at Austin
University of Lucknow
Recommendations: 0
a****[email protected]
Shadi Youssef
Principal Engineer
San Jose, California
Principal Engineer
RFIC Design Engineer
Senior Staff RF System Engineer
University of Twente
Aalborg University
Ain Shams University
Recommendations: 0
RF circuits
Analog Circuit Design
Power Amplifiers
CMOS
Research
Layout
Semiconductor Industry
Wireless
s****[email protected]
Ghazaleh Mirjafari
Sr. Staff IC Design Engineer
San Jose, California
Sr. Staff IC Design Engineer
San Jose State University
Iran University of Science and Technology
Recommendations: 0
ModelSim
Xilinx
Verilog
FPGA
Static Timing Analysis
Perl
Digital Design
Integrated Circuit...
g****[email protected]
Souchkov Vitali
Senior IC Design Engineer
San Jose, California
Senior IC Design Engineer
Senior Engineer/Physicist
Principal Consultant
Senior Engineer/Physicist
Physicist Scientist/Engineer
Principal Member of Technical Staff
Project Associate
Researcher
Research and Development IC Design Engineer
Project Associate
Moscow Institute of Physics and Technology (State University) (MIPT)
Recommendations: 0
Semiconductors
IC
Analog
Electronics
Simulations
Sensors
CMOS
Mixed Signal
v****[email protected]
Kin Au
IC Design Section Head
San Jose, California
IC Design Section Head
SoC Design Engineer
Senior Staff IC Design Engineer
Staff IC Design Engineer
Advanced IC Design Engineer
IC Design Manager
IC Design Engineer
Intern
Senior IC Design Engineer
ASIC Digital Design Engineer
Universiti Teknologi Malaysia
Recommendations: 0
ASIC
Static Timing Analysis
RTL design
Integrated Circuit Design
FPGA
DDR
SPICE
PHY
a****[email protected]
Sagar Ray
Analog/RF IC Design Engineer
San Jose, California
Analog/RF IC Design Engineer
Design Engineering Intern
Sr. Analog/RF IC Design Engineer
Sr. Staff Analog IC Design Engineer
Design Engineering Intern
Research Assistant
Teaching Assistant
Sr. Analog/RF IC Design Engineer
Rensselaer Polytechnic Institute
Bangladesh University of Engineering and Technology
Recommendations: 0
Analog Circuit Design
Matlab
CMOS
C++
Mixed-Signal IC Design
Electrical Engineering
Cadence Spectre
Agilent ADS
s****[email protected]
Roger Karam
Principal Hardware Engineering -Consulting Projects
San Jose, California
Principal Hardware Engineering -Consulting Projects
VP of Technology- Smart Watch with Cloud Platform
Principal Staff Engineer
Tech Lead | Catalyst 6K (IoT Business Group)
Director of Signal Integrity. (High Speed Group)
Tech Lead | VOIP Telephony
Hardware Engineer
Tech Lead | Catalyst 2K/3K Business Group
Custom Analog IC Design Engineer
San Jose State University
College of San Mateo
Recommendations: 0
Signal Integrity
ASIC
Ethernet
Embedded Systems
Hardware
Integrated Circuit Design
SPICE
Wireless
r****[email protected]
z****[email protected]
David Pan
Design Verification Engineer
San Jose, California
Design Verification Engineer
Staff Design Engineer
Sr. Technical Lead & Architect / Sr. Staff Design Engineer
Design Lead / Senior RTL Design Engineer II
ASIC Design Engineer
University of Southern California
Recommendations: 0
c****[email protected]
Mamatha Deshpande
Senior Staff Analog Engineer
San Jose, California
Senior Staff Analog Engineer
Senior Analog Design Engineer
Staff Design Engineer
Senior Member of Technical Staff
IC Design Engineer
University of Central Florida
Rashtreeya Vidyalaya College of Engineering, Bangalore, India
Recommendations: 0
ASIC
Semiconductors
IC
CMOS
Mixed Signal
Integrated Circuit Design
SoC
Analog Circuit Design
m****[email protected]
Javad Mahdavi
Associate Professor
San Jose, California
Associate Professor
Staff Design Engineer & Project Lead
Member of Technical Staff, Analog IC Design
Principal Analog IC Design Engineer
Member Of Technical Staff Analog IC Design
Senior Staff Design Engineer
Director of Design and Staff Design Engineer
Sharif University of Technology
Institut polytechnique de Grenoble
Recommendations: 0
IC
Power Management
CMOS
Electronics
Power Electronics
ASIC
Circuit Design
Mixed Signal
j****[email protected]
Miro Svajda
Analog&Mixed-Signal IC Design Consultant
San Jose, California
Analog&Mixed-Signal IC Design Consultant
Staff Analog IC design engineer
Senior analog IC design engineer
Analog Design Engineer
Staff Analog IC Design Engineer
Brno University of Technology
Recommendations: 0
CMOS
Semiconductors
Integrated Circuit Design
Debugging
Simulations
SoC
Mixed Signal
Primetime
o****[email protected]
Xiang Guo
Software Engineer
San Jose, California
Software Engineer
Senior Design Engineer
ASIC Design Engineer
Master Degree
Research assistant
Stony Brook University
Southeast University
Recommendations: 0
Matlab
C++
Microsoft Office
Excel
Word
PowerPoint
VHDL
Mathematica
g****[email protected]
Gaurav Mittal
Member Of Technical Staff
San Jose, California
Member Of Technical Staff
Sr Design Engineer
ASIC Design Engineer
Jr Engineer
Principal Engineer
Senior Design Engineer
The University of Texas at Arlington
Kurukshetra University
Recommendations: 0
VLSI
HSPICE
Verilog
System Verilog
RTL design
HSIM
Perl
Assertion Based Verification
g****[email protected]
Hossein Lavasani
Sr. Staff RF/Analog IC Design Engineer
San Jose, California
Sr. Staff RF/Analog IC Design Engineer
Staff RF/Analog IC Design Engineer
Analog IC Design Engineer IV (R&D)
IC Design Engineer
Assistant Professor
Graduate Research Assistant
Research Assitant
Georgia Institute of Technology
Arizona State University
Sharif University of Technology
Recommendations: 0
RF/Analog IC Design
MEMS and Sensors...
Circuit Design
Integrated Circuit...
MEMS
R&D
Simulations
Low-power Design
h****[email protected]
Krishna Vummidi
Senior MEMS Design Engineer
San Jose, California
Senior MEMS Design Engineer
RFIC Design Engineer
Lecturer
RF-MEMS/RFIC Graduate Research Assistant at Wireless Microsystems Lab
RF-MEMS Design Engineer - Co-op (Corp. R & D)
Virginia Polytechnic Institute and State University
University of Cincinnati
Sathyabama Institute of Science and Technology
Recommendations: 0
Simulations
MEMS
IC
Electronics
Analog Circuit Design
Testing
Electrical Engineering
Circuit Design
k****[email protected]
Zhichong Liu
Staff Design Engineer
San Jose, California
Staff Design Engineer
ASIC Design Engineer
ASIC Design Engineer
University of Florida
Huazhong University of Science and Technology
Wuhan Foreign Languages School
Recommendations: 0
ASIC
RTL design
Baseband
Verilog
Physical Design
Formal Verification
Timing Closure
Static Timing Analysis
a****[email protected]
Morgan Teachworth
VP of Engineering
San Jose, California
VP of Engineering
Director, Hardware Engineering
Manager, Hardware Engineering
Team Lead, Hardware Engineering
ASIC Design Engineer
Senior Director, Product Engineering and Hardware Operations, Global Sourcing and Supply Chain
Hardware Program Manager
Financial Officer, Governor's Corner Bollard Dining Society
Stanford University Graduate School of Business
Stanford University
Recommendations: 0
m****[email protected]
m****[email protected]
Helen Zhang
Lead RFIC Design Engineer
San Jose, California
Lead RFIC Design Engineer
University of Washington
University of Washington
University of California, Berkeley
Recommendations: 0
h****[email protected]
h****[email protected]
Shah Sharif
Analog Mixed Signal IC Design Engineer
San Jose, California
Analog Mixed Signal IC Design Engineer
Senior Principal Engineer
Principal Design Engineer
Analog Mixed Signal IC Design Engineer
Analog Mixed Signal IC Design Engineer and Architect
Principal Engineer
University of California, Los Angeles
Arizona State University
Recommendations: 0
Analog
Mixed Signal
Verilog
ASIC
RF
Integrated Circuit Design
Cellular Communications
CMOS
s****[email protected]
Paul Chang
Senior Project Manager
San Jose, California
Senior Project Manager
Senior Design Engineer
Senior Design Engineer
Senior Principal IC Design Engineer
Digital Design Engineer
Senior Design Engineer
Design Engineer
Senior Principal IC Design Engineer
UC Santa Barbara
National Taiwan University
Chien Kuo High School
Recommendations: 0
SoC
ASIC
Functional Verification
ARM
EDA
TCL
SystemVerilog
RTL design
p****[email protected]
p****[email protected]
Ausaaf K.
Sr CPU Logic Design Engineer
San Jose, California
Sr CPU Logic Design Engineer
ASIC Design Engineer
CPU Logic Design Engineer
ASIC Design Engineer
CPU Logic Design Engineer
The University of Texas at Austin
Oklahoma State University
Recommendations: 0
ASIC
Verilog
SystemVerilog
RTL design
Logic Design
Static Timing Analysis
VLSI
Timing Closure
a****[email protected]
David Nadell
Hardware Design Engineer
San Jose, California
Hardware Design Engineer
Hardware Design Engineer
ASIC Design Engineer
Senior Component Design Engineer
RTL Design Engineer
Senior Digital Design Engineer
Hardware Design Engineer
California State University, Sacramento
Recommendations: 0
d****[email protected]
Gordon Kwan
Realtor
San Jose, California
Realtor
ASIC Design Engineer
Senior Electrical Engineer
FPGA Design Engineer
Co-Founder, VP Hardware Engineering
University of California, Los Angeles
USC
Recommendations: 0
FPGA
Verilog
Semiconductors
Embedded Systems
Hardware Architecture
RTL design
SoC
VHDL
g****[email protected]
Junho Cho
Analog IC Engineer
San Jose, California
Analog IC Engineer
Senior Analog and Mixed Signal IC Design Engineer
Staff Analog and Mixed Signal IC Design Engineer
Associate Principal Analog and Mixed Signal IC Design Engineer
Senior Staff Analog and Mixed Signal IC Design Engineer
Sogang University
Sogang University
Recommendations: 0
Mixed Signal
Timing Closure
EDA
CMOS
Debugging
Semiconductors
Circuit Design
Static Timing Analysis
j****[email protected]
Avinash Gupta
Senior Staff Engineer, ASIC Design
San Jose, California
Senior Staff Engineer, ASIC Design
Senior ASIC Design Engineer
Microarchitect Engineer
Senior ASIC Design Engineer
R & D Engineer
Design Engineer Principal
Design Engineer Staff
Design Engineer Sr.
ASIC Design Engineer
ASIC Verification Intern
New Mexico State University
Recommendations: 0
SystemVerilog
Verilog
RTL design
SoC
ASIC
Debugging
Functional Verification
VLSI
g****[email protected]
William Tang
Senior Staff RFIC Design Engineer
San Jose, California
Senior Staff RFIC Design Engineer
Analog Design Engineer
Principal RFIC Design Engineer
Staff II RFIC Design Engineer
University of California, Los Angeles
The University of Texas at Austin
National Junior College
Recommendations: 0
RF
Mixed Signal
w****[email protected]
Charles Chen
Staff RF/mm-wave IC Design Engineer
San Jose, California
Staff RF/mm-wave IC Design Engineer
Analog System Design Engineer
Senior RF/mm-wave IC Design Engineer
RF/mm-wave IC Design Intern
Research Assistant
RF System Design Intern
Rice University
Purdue University
The University of Texas at Austin
Recommendations: 0
Circuit Design
Analog Circuit Design
PCB Design
CMOS
Antennas
RF & Microwave Design
Mixed-Signal IC Design
Cadence Virtuoso
s****[email protected]
Ka Kwok
RFIC Engineer
San Jose, California
RFIC Engineer
Research Scientist
Analog IC Design Engineer
Analog RFIC Design Expert
RFIC
Technische Universiteit Delft
The Hong Kong University of Science and Technology
The Hong Kong University of Science and Technology
Recommendations: 0
IC
Electronics
RF
Integrated Circuit...
Wireless
CMOS
Analog
ASIC
e****[email protected]
Onder Oz
Analog Design Engineer
San Jose, California
Analog Design Engineer
Engineering Manager
Principal Analog/RF IC Design Engineer
Staff Analog/RF IC Design Engineer
Senior Analog IC Design Engineer
RF/Analog IC Design Engineer
RF IC Design Engineer
Teaching Asistant
Intern Engineer
University of Southern California
University of Southern California
Recommendations: 0
h****[email protected]
Xueqing Wang
Analog IC Design Engineer
San Jose, California
Analog IC Design Engineer
Analog design engineer
Analog/mixed signal design and data converter testing (including intern experience)
University of Florida
Huazhong University of Science and Technology
Recommendations: 0
Analog Design
Mixed Signal
Integrated Circuit...
4****[email protected]
nayankumar navadiya
ASIC Design Engineer
San Jose, California
ASIC Design Engineer
Centre for Development of Advanced Computing
Veer Narmad South Gujarat University, Surat
Recommendations: 0
DFT Compiler
Physical Design
Logic Synthesis
Static Timing Analysis
Physical Verification
DFT
DRC
ASIC
n****[email protected]
Mishra Vineet
Principal Mixed Signal Engineer
San Jose, California
Principal Mixed Signal Engineer
Senior IC Design Engineer
Design Manager &Technical Lead
Indian Institute of Technology, Kanpur
Recommendations: 0
Low Power Design
Analog Design
Analog Circuit Design
Analog
Low-power Design
Integrated Circuit Design
Mixed Signal
SoC
v****[email protected]
David Lamb
Acoustic Test System Engineer
San Jose, California
Acoustic Test System Engineer
Senior Principal Design Engineer
R&D IC Design Engineer
Senior Digital Design Engineer
Analog Characterization Engineer
Universidade de São Paulo / USP
Northeastern University
McGill University
Recommendations: 0
Chun-Sup Kim
Electronic Design Engineer - SPE
San Jose, California
Electronic Design Engineer - SPE
Principal RF Analog/Mixed Signal IC Design Engineer
Distinguished Analog/Mixed Circuit Engineer
Principal Analog/Mixed IC designer
Korea University
Recommendations: 0
Rupesh Parab
Sr ASIC Design Engineer
San Jose, California
Sr ASIC Design Engineer
Sr Staff Digital Design Engineer
Graduate Research Assistant
Graduate Research Assistant
Senior Digital Design Engineer
Digital Design Engineer
Technical Head
Senior Digital Design Engineer
Georgia Institute of Technology
K. J. Somaiya College of Engineering, University of Mumbai
Recommendations: 0
Garett C.
Sr Staff Design Engineer
San Jose, California
Sr Staff Design Engineer
Senior R&D Engineer II
Senior R&D Design Engineer
ASIC Design Engineer
ASIC Design Engineer
ASIC Design Engineer
Applications Engineer
University of California, Davis
Recommendations: 0
Boris L.
Sr. ASIC Engineering Manager
San Jose, California
Sr. ASIC Engineering Manager
Sr. ASIC Design Engineer
Staff ASIC Design Engineer
Sr. Staff Design Engineer
Lead ASIC Design Engineer
Sr. Design Engineer
Portland State University
University of Houston
Georgia Institute of Technology
Recommendations: 0
Sage Kim
FPGA/ASIC Design Engineer
San Jose, California
FPGA/ASIC Design Engineer
Head of Research and Development
Senior R&D Engineer
Senior R&D Engineer
Staff Design Engineer
Korea Advanced Institute of Science and Technology
Dongguk University
Recommendations: 0
Ahmed Abdelmoaty
Staff Analog IC Design Engineer
San Jose, California
Staff Analog IC Design Engineer
Research Assistant
Graduate Research Assistant
PhD Candidate / Graduate Research Assistant
Senior Analog IC Design Engineer
Intern - Intel Labs (Power Delivery Research)
Intern
Intern - Power Management IC Design Group
Research Assistant
The Ohio State University
Iowa State University
The American University in Cairo
Recommendations: 0
John Thodiyil
Principal SOC/ASIC architect/design engineer
San Jose, California
Principal SOC/ASIC architect/design engineer
Principal ASIC Design Engineer
Senior SOC/ASIC Design Engineer
Founding Director/Architect of SOC/ASIC development
MTS ASIC design Engineer
Founding Director/Architect of SOC/ASIC development
Stanford University
Recommendations: 0
Ting Qu
Principal Verification Engineer
San Jose, California
Principal Verification Engineer
Principal Verification Engineer
ASIC Design Engineer
Senior Staff Design Verification Engineer
Principal Verification Engineer
University of Colorado Colorado Springs
University of Colorado Colorado Springs
Recommendations: 0
Sanketkumar Parekh
FPGA Engineering Trainee
San Jose, California
FPGA Engineering Trainee
FPGA Design Engineer
Senior ASIC Design Engineer
Student Assistant
San Jose State University
CHAROTAR UNIVERSITY OF SCIENCE AND TECHNOLOGY
Recommendations: 0
