I am currently looking for a engineering position were i can contribute to a companies success. My area of expertise is the Modelling and implementation of digital signal processing (DSP) algorithms in Verilog / SystemVerilog, or DSP processor dependent assembly language, or Matlab, or embedded 'C' programming. That is i implement algorithms in ASICs, FPGAs, or DSP processors programs.

Principle ASIC Design Engineer @ I work in the “High Performance 16-bit Micro-Controller” group that produces the dsPIC and PIC24 line of product. I contribute in the development of derivative chip that are the newest line of 16-bit micro-controllers produced by Microchip. My duties encompass all the areas of front-end ASIC development. I write some RTL code to implement design variations; Trouble shoot regression test if they start failing; Investigate application problems by RTL simulation or writing custom assembly language test to find problem areas: I participate in design reviews of many types including architecture changes and chip layout; I do power simulations using Prime-Time PX. I help in keeping the overall process going to turn out highly successful micro-controller at the rate of five or more new variants per year. From October 2010 to May 2014 (3 years 8 months) Sr. Digital Audio ASIC Design Enginee @ I was responsible for digital audio signal processing for the company’s wireless audio ASICs. Including the gathering of requirements, definition of chip micro-architectures, modeling the DSP functions in Matlab, coding the Verilog, coding test benches, running chip simulations, compiling the designs into Altera FPGAs for prototyping and system integration and testing. I designed and implemented the digital IIR filters for speaker crossovers and speaker equalization. I also designed the digital FIR filters and decimators for sample rate conversions. My work was 40% of the Summit Wireless chip FS848. From July 2008 to February 2010 (1 year 8 months) Staff Digital Audio ASIC Design Engineer @ I was responsible for the receiver audio section of an ASIC that integrates an 802.11a base-band processor, NIOS II embedded processor and 24-bit high quality audio processing for a wireless home theater surround sound system. The audio section performed streaming error concealment, three band equalization, speaker driver equalization, three band mixing, volume controls, and pop filtering all with 135 dB of dynamic range. The digital filters are a combination of FIRs and IIR Second-Order-Sections required meeting stringent pro-audio 24-bit quality with minimum group delay. This architecture included up and down sampling blocks with a self-timing ‘push’ data path. All filters were loadable from the embedded NIOS processor. I implemented the code in Verilog RTL, simulated with NC-Verilog, modeled the DSP functions with Matlab, and designed the filter coefficients per the required response specifications. This was a wonderful start up. From December 2006 to August 2007 (9 months) Staff FPGA/ASIC Design Engineer @ Responsible for implementation of a sub-rate 16k, 32k, and 64k bits/second multiplexing FPGA used to move data from ATM links to/from T1/E1 links. I did the detailed design specification and the macro and micro FPGA architecture to meet design specifications. I interfaced with circuit board developers and customers to ensure the design specification would meet the needs of the overall project. I interfaced with Software teams to ensure a smooth HW/SW interface and interaction with the FPGA. I identified opportunities for the use of external IP to speed up development time. I negotiated with external IP houses for the best contract terms. I did RTL development for all stages of implementation and verification. I specified the test environment to ensure a completely operational and fully tested device for production delivery. I developed all bus functional models and other behavioral RTL code in support of the testing environment. I worked to determine the overall schedule for the entire FPGA project. I managed the work and schedule for junior engineers. I provided constant feedback to the board designers about the FPGAs impact to board design (signal integrity, etc.). I wrote scripts to support post processing of test data. I improved the design and test process in general. I also participated in the development and maintenance of an internal company IP group. Went to a wonderful start up. From September 2005 to December 2006 (1 year 4 months)

Graduate classes in Linear Active Network and Digital Signal Processing, 3.5 out of 4.0 @ Stanford University Graduate classes in Linear Active Network and Digital Signal Processing From 1977 to 1979 Bachelor's Degree, 3.8 out of 4.0 @ DeVry Institute of Technology, Phoenix, Az (ABET Certified) From 1973 to 1976 Richard Johnson is skilled in: • CSR Kalimba 8670 Assemble language programming and debug, • DSP implementation with Verilog RTL derived from signal flow diagrams, differe, • Digital IIR, FIR, polyphase, decimators, interpolators, and error concealment, • Proficient with lab equipment: Scopes, Logic State Analyzers (LSA), Spectrum A, • Experience with geographically dispersed working groups (India, Arizona, Color, • Leader of RTL group for the development of a digital radio receiver ASIC, • Leader of hardware development of the Boeing 777 airplane “Flight Line Validat, • Altera Quartus, Modelsim, Synplify Pro, Matlab, Verilog, SystemVerilog, Python, FPGA full cycle development, ASIC front end & verification development, System architecture and micro-architecture requirements, partitioning, and spe, Verification using self-checking test-bench methodologies in Verilog, SystemVe, Quality of Service (QoS) packet scheduling through dynamic memory buffer alloc