Senior Pre-Si Verification/Validation Engineer at Intel Corporation
Portland, Oregon
Senior Pre-Si Verification/Validation Engineer @ Intel Corporation Portland, Oregon AreaDesign Verification Consultant at Intel Corporation @ Wipro Verification of Memory Controller ASICVerification of Networking Series chipset for Data CentersVerification of SoCs for next generation smartphones/tabletsUsed SystemVerilog and methodologies like OVM,UVMCoded SV assertions From September 2012 to April 2017 (4 years 8 months) Santa Clara, CADesign Verification Consultant...
Senior Pre-Si Verification/Validation Engineer @ Intel Corporation Portland, Oregon AreaDesign Verification Consultant at Intel Corporation @ Wipro Verification of Memory Controller ASICVerification of Networking Series chipset for Data CentersVerification of SoCs for next generation smartphones/tabletsUsed SystemVerilog and methodologies like OVM,UVMCoded SV assertions From September 2012 to April 2017 (4 years 8 months) Santa Clara, CADesign Verification Consultant at Cisco Systems @ Wipro Worked on block and chip level verification of a Multiport Ethernet switch ASIC.Worked on gate-level simulations for the Ethernet switch ASIC netlistsWorked on functional coverage and coded coverpoints.Contributed to the proposal making for a Cost Reduction Ethernet Linecard. Evaluated the BOM for the existing board for equivalent RoHS compliant components. Evaluated the existing code in the FPGA for redundant logic in order to target smaller FPGA to reduce cost. Worked on the estimates for the manhours required for various activities. Made significant savings in terms of cost per PCB board.Used VERA and SystemVerilog.Worked on methodologies like RVM,OVM Extensively used VCS, debugging tools like Debussy,DVE From March 2006 to August 2012 (6 years 6 months) Bangalore,IndiaDesign Verification Consultant at Thomson Inc @ Celstream Technologies Full chip verification of 2D graphics processor and compositor intended to go inside a set top box.Testcase development for interlaced and progressive scanning scenarios in VerilogDesign and verification of blocks inside the Ethernet Transmit/Receive Host Interface of a Packet Processor ASICDeveloped a MAC Processor BFM in VHDL, which basically stores MAC entries and does a search of the MAC address in the MAC entity tableExtensively used Verilog and VHDL.Hands-on experience with Synopsys Design Compiler From January 2003 to February 2006 (3 years 2 months) Bangalore, IndiaDesign Engineer @ VXL Instruments Design, implementation and verification of Bit Error Rate tester using Verilog, prototyped into a Xilinx 95XC288XL CPLD and validated using a DSL modem.Extensively used Mentor Graphic tools for verification.Used design entry tools from Synplicity.System validation of Thin Clients using various operating systems. From September 2000 to January 2003 (2 years 5 months) Bangalore, India
Intel Corporation
Senior Pre-Si Verification/Validation Engineer
Portland, Oregon Area
Wipro
Design Verification Consultant at Intel Corporation
September 2012 to April 2017
Santa Clara, CA
Wipro
Design Verification Consultant at Cisco Systems
March 2006 to August 2012
Bangalore,India
Celstream Technologies
Design Verification Consultant at Thomson Inc
January 2003 to February 2006
Bangalore, India
VXL Instruments
Design Engineer
September 2000 to January 2003
Bangalore, India
What company does Jena Abraham work for?
Jena Abraham works for Intel Corporation
What is Jena Abraham's role at Intel Corporation?
Jena Abraham is Senior Pre-Si Verification/Validation Engineer
What industry does Jena Abraham work in?
Jena Abraham works in the Semiconductors industry.
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