Hung Nguyen's Email Addresses & Phone Numbers

📖 Summary

Sr. Display Electrical Engineer @ Apple Sr. Hardware Engineer @ Infinera From November 2009 to September 2013 (3 years 11 months) Sr. Hardware Engineer @ Brilliant Telecommunications Designed the GPS based outdoor NTP server using POE.Wrote hardware functional and performance requirements, hardware specification and DVT plan.Generated schematic, netlist and define PCB layout instructions.Performed DVT and resolve EMI issues and released documents to production.Designed time and synchronization master with 2.5KV isolation I/O requirements for power industryDesigned OEM timing packet processor to support GPS/GLONASS:Duties include writing hardware specification and performed DVT; debug and bring up the module.Analyzed and qualified time and synchronization aspects (jitter, wander, MTIE, TDEV) in packet network per. ITU G.8261 From December 2004 to September 2009 (4 years 10 months) Sr. Hardware engineer @ Ciena • 1.25Gbps, 64 Channels Switch Module Electrical DesignerCreated functional and performance module requirements; Wrote hardware module specification, test specification and DVT plan; Responsible for the module from design through the production release. Board design: Generated schematic, net list for PCB layout; Performed SSO analysis on 125Mhz SSTL-2 drivers; Performed HSPICE simulation on 1.25Gbps CML drivers on different SerDes Chips; Evaluated and Selected the 1.25Gbps SerDes chip; Proposed 24 layers PCB stack-up, and Created layout instructions; Worked with PCB designer to specify layout constraints for auto-route tool.Engaged FPGA/CPLD design: 2xFPGAs Spartan II E and 1x CPLD Cool runner devices provide control and monitor functions for the switch card such as processor interface, Back door test interface, Serial interface with Switch Chip, MDIO interface to configure SerDes chips, in system programming interface, I2C interface, etc.• Timing Module DVT Design SupporterWrote and Performed DVT plan for timing module. The timing module provides synchronization for the whole optical switch system. Tasks involved PLLs design and verification, FPGA timing controller verification. From August 2002 to September 2003 (1 year 2 months) Hardware Development Engineer @ Caspian Networks • 8x1Gige Ports Line Card Electrical DesignerWorked with system architect to create the hard ware design specificationBoard design : Generated schematic, net list for PCB dimension 13x20 28 layers; Set electrical constraints in schematic and provide PCB layout guidance for high speed signal up 320Mhz; Performed signal integrity analysis.Engaged FPGA design: The slow path controller in Virtex 600E provides major functions for the line card: An interface to the SDRAM memory local to Power PC750 500Mhz, ECC checking and generation, an PCI interface to two AMD 79C975 Ethernet 100 base controller chips and an Ethernet switch Broadcom chip, an PCI like to boot controller, arbitration logic, interrupt controller and other miscellaneous interfaces Created test bench at board level to simulate and verify all interfaces Worked with software drivers to perform hardware diagnosticCreated bring up procedure• 4xOC 48 Line Card Design Supporter Performed traffic test on OC48 linecard with different IP packetsEvaluated 4xOC48/OC192 Ganges performanceEvaluated new OC48 transceivers and suggested the circuitry to monitor Tx Power Designed 16bit CPU interface with the Ganges chipDesigned the burst access between slow and fast path controllerModified the decoder in SDRAM controller to support misaligned memory accessGenerated packet generator load for 2600 Virtex to test Myricom-Switch Fabric ChipUsed VISION ICE to debug power PC, Sdram and other interfaces in the OC48 line cardProvided technical guide to Lab staff to debug and test OC48 Line CardCreated bring-up procedure and script to test the OC48 line card• Supper IP switch Back plane electrical designerThe 19x20 Back plane is the house for 16 Line card and 2 redundant supervisor cards. It provides the high speed fabric link between line cards and shelves.Set electrical constrains for high speed signals (LVDS 320Mhz) From June 2000 to July 2002 (2 years 2 months) Hardware Development Engineer @ Harris Microway Communication • Developed multiplexers for microwave digital communication systems• FPGA design: Designed high level mux/demux for clear channel DS3 and services channels• FPGA design: Designed high level mux/demux for DS3 plus DS2 and services channels• Designed second order PLL to synchronize different clock domains.• Board design: Worked on schematic capture, component selection, layout guidance for the Access Control Unit. The Unit takes OC3 mux/demux with T1, E1 and wayside and sends the signal to the modem. It also includes a PowerPC MC68360QUICC to provide control and monitor functions.• Performed jitter and wander test on DS1, DS3, OC3 per BELL CORE From July 1998 to June 2000 (2 years)