President @ Independent ASIC/FPGA Design, Verification and Embedded Software Consultant. From July 2006 to Present (9 years 6 months) FPGA Design and Verification Consultant @ RTL design, verification and test of a Microsemi SmartFusion2 SoC with on-chip FPGA and ARM Cortex-M3 subsystem for Guided Wave and Acoustic Emission data acquisition and analysis. Designed an AXI data pump for burst write of the 8 channel acquisition data to the DDR3 memory, as well as an AHB DMA Engine with DSP capabilities for signal processing of the acquisition data. Synthesized the design and closed timing using the Libero toolchain. Created a verification testbench using the table-driven DAC interface to stimulate the FPGA using ModelSim. Debugged the FPGA board and C++ driver software using traditional lab equipment and simulation. From November 2014 to Present (1 year 2 months) Director of IC Design Services @ Hands-on leadership role for SoC/IC design and verification projects. Building a high quality development team of onshore and offshore engineers for projects with blended teams. When not working on customer projects, working on internal RTL and DV IP programs. From September 2013 to November 2015 (2 years 3 months) Verification Consultant @ ASIC Verification of the Host Interface subsystem of a 100Gbps optical networking device. Wrote constrained random tests in C++ with a Teal and Truss object oriented framework. Created new tests, as well as modified existing tests and randomization constraints at the block and system level. Tested two ARM Cortex-R4F CPUs, program and data memories, AXI bridge, MDIO, SPIs, I2Cs, UARTs and other host peripherals using Synopsys VCS/DVE. Collected and analyzed coverage results for all blocks tested. From April 2014 to September 2014 (6 months) Verification Consultant @ Designed the RTL and verified an OTP Controller for a MIPI CSI-2 TX image sensor ASIC using System Verilog and Verilog. Enhanced the System Verilog mixed signal image sensor simulation model. Ported the home-grown TCL and Verilog verification test code to System Verilog. Added an object oriented error handler and image capture and test monitors along the image pipeline of the system level testbench. Started porting the system level testbench to UVM and completed the driver layer before the activity was suspended by higher priorities. Collected and analyzed coverage data for all blocks using the Cadence Incisive tools. From September 2013 to April 2014 (8 months) Hardware Engineer Consultant @ RTL Design and Verification of demonstration FPGAs for a 4Mbps GMSK modem. Created a programmable packet generator with a LFSR payload and FEC tags as well as a multi-lane packet receiver to verify the received content. Integrated a digital noise generator into a multi-lane channel subsystem for BER testing. Verified the design using ModelSim and debugged several functional issues with the GMSK modem DSP subsystem. Synthesized the design and completed timing closure using Vivado tools. Tested the implementation on a Xilinx Virtex 7 Quickstart board using LabTools. Correlated the BER results of the FPGA and simulations with the C-code model of the modem. Created an Expect/TCL script to automate the testing. From March 2013 to July 2013 (5 months) Director, Business Development @ Developed business relationships for mobile operating system ports and GPU drivers for mobile devices. From February 2012 to July 2012 (6 months) Senior Program Manager Consultant @ Program Manager for the Handheld Graphics Processor Unit (GPU) IP business. Debugged several issues found with the Freescale i.MX5x 3D GPU drivers and GPU microcode, as well as debugged the 2D GPU Verilog RTL precision issues. Managed the third party development of the driver code through Agile/Kanban methods. Worked with ARM on the integration of AMD GPUs with ARM CPUs for mobile applications. Program Manager for the GPU Backwards Compatibility features for a next generation game console. From November 2008 to December 2011 (3 years 2 months) Verification Consultant @ Verification Consultant for a crossbar switch of a fault tolerant computer. Modified an existing PCI Express 1.1 test code to PCI Express 2.1 using System Verilog, Vera, Verilog and C++ within a Synopsys RVM environment. Modified the Verilog physical model to comply with the PCI Express 2.1 specification. Modified the System Verilog block level test to verify the state and initialization changes. Modified the RVM and Vera interrupt manager/scoreboard to be consistent with changes in the design. From April 2008 to October 2008 (7 months) Consulting Software Engineer @ Created serial port device drivers and embedded software in C and Assembly Language with RTX51 for the manufacturing test interface of a wireless HDMI SoC. From June 2007 to February 2008 (9 months) Consulting Systems Engineer @ Performed research and conceptual design of an Alert Enabled Device utilizing Satellite Messaging, Cellular Phone and Global Positioning System (GPS) technologies. Co-authored the final report. From April 2007 to June 2007 (3 months) Verification Consultant @ Created the self-checking module level test code for the 8051 subsystem of a wireless HDMI SoC using System Verilog, Verilog and C/C++ within a home-grown framework. Created a system level testbench with transmitter and receiver instantiations of the device for end to end testing. Debugged the bootloader firmware and the runtime software using the system level testbench. Created the production test code and generated the manufacturing test vectors. Back annotated the post-route timing data and verified the design. Integrated the HDCP “C” algorithm via the DPI to test the RTL design. From July 2006 to March 2007 (9 months) Director of Engineering @ Managed several USB PHY development projects. Debugged issues with the Verilog testbench. From May 2006 to July 2006 (3 months) VP, IP Engineering @ Managed the development of a USB OTG/Host ASSP. Wrote the C++ post-silicon test code using VxWorks. From June 2004 to February 2006 (1 year 9 months) Director of Engineering & Operations @ Managed an IP development team for USB, 802.3, industry standard processors and other peripherals. Managed the import of third party WIFI and IPSEC RTL and DV IP blocks. Evaluated and purchased a verification framework from Qualis (later became the VMM) to augment the supplier test code. Worked with two outsourced DV engineers to integrate and test the WIFI IP. From August 2002 to June 2004 (1 year 11 months) Technical Manager @ Hands on Site Manager for a sixteen person design services organization. From June 1997 to July 2002 (5 years 2 months) AMS Modeling Consultant @ Modeled the discrete board power supply behavior via SPICE for a test board for a 2GHz RISC processor. Assisted with the board level signal integrity analysis of the DDR400 interface. From March 2002 to June 2002 (4 months) FPGA Verification Consultant @ Debugged the Verilog test environment for the ATM FPGA. From September 2001 to March 2002 (7 months) Project Manager Consultant @ Architecture of a PowerPC-based set top box controller board. From November 2000 to April 2001 (6 months) FPGA and Board Design Consultant @ Developed the VHDL RTL for an image acquisition FPGA and coordinating PCI controller board for a machine vision subsystem. From April 2000 to October 2000 (7 months) Verification Consultant @ Developed the VHDL RTL for an Audio/Video datapath FPGA for a non-linear production recording deck with a proprietary disk interface. Developed the VHDL RTL for an Audio/Video datapath FPGA for a non-linear production camera that incorporated a third party PCI controller block for the disk interface. Created simulation environments using the FPGA development tools to debug the RTL. From May 1997 to March 2000 (2 years 11 months) VP, HW Engineering @ Co-founder of an image enhancement technology startup company. Co-inventor of an image enhancement technology for laser printers based on spatial frequency analysis. Developed several prototype FPGAs, boards and software. From January 1995 to August 1997 (2 years 8 months) Director of OEM Engineering @ Co-developed the algorithms for a proprietary image enhancement technology and created the RTL in VHDL. Created a gray box test code for correlation with the software model. Designed several test and development platform boards based on Xilinx FPGAs. From October 1992 to December 1994 (2 years 3 months) Manager, Print Systems @ Designed an OCR subsystem with Feature Extraction and Vector Correlation. Designed four laser printer controllers for printers ranging from 8ppm to 50ppm. Developed several ASICs and FPGAs for image processing, image enhancement, rasterop assist and multiport rasterop memory control. From April 1983 to August 1992 (9 years 5 months) Group Leader @ Designed a production debug system based on signature analysis for a console facsimile machine. Redesigned a full duplex facsimile controller board replacing the dual 1-bit microprocessor with a dual 6802. Designed a dual 6809 controller board for a console facsimile machine. Designed a 12ppm laser printer controller based on a 29116 bit slice implementation of a 68000 with graphics assist instructions and hardware rendering engine. Wrote the microcode for the 68000 instruction set and the graphics instructions. Worked on an image compression and decompression ASIC. From June 1979 to April 1983 (3 years 11 months)

BS, Electrical and Computer Engineering @ Clarkson University From 1975 to 1979 Waterford-Halfmoon High School From 1970 to 1975 Gene Chouiniere is skilled in: FPGA, ASIC, Verilog, Debugging, Processors, Embedded Systems, C, C++, ARM, Firmware, Embedded Software, Device Drivers, Linux, Software Development, VHDL