Bachelor’s Degree, Electrical, Electronics and Communications Engineering @
Wuhan University
About:
No longer working on ASIC/FPGA Design and Verification directions.
As a full stack engineer, majorly focusing on end to end website development and online recommendation systems design and implementation with widely interesting on Data mining and Big data/Apache Spark.
Personal Blog: https://chongyaorobin.wordpress.com/
Github: https://github.com/ZaphyrRobin
Software Engineer @ Product design/UI design and implement of several subsystems on https://www.yapjoy.com/ from
No longer working on ASIC/FPGA Design and Verification directions.
As a full stack engineer, majorly focusing on end to end website development and online recommendation systems design and implementation with widely interesting on Data mining and Big data/Apache Spark.
Personal Blog: https://chongyaorobin.wordpress.com/
Github: https://github.com/ZaphyrRobin
Software Engineer @ Product design/UI design and implement of several subsystems on https://www.yapjoy.com/ from back-end to front-end using Bootstrap, HTML5, jQuery, Ajax on Django framework deployed on Heroku and AWS S3. Particularly design and program social-relationship driven recommendation system algorithm and fulfill its data visualizations using D3.js. From August 2015 to Present (5 months) ASIC Verification Consultant @ Built unit level verification environment in UVM for three IPs and write full chip level tests in C for D7 H.265 (HEVC) Video Baseband processing FPGA Chip. Code system level scripts in Perl and generate test-vectors in Python. From September 2014 to August 2015 (1 year) ASIC Verification Engineer @ Developed unit level verification environment for CAVLC block for H.264 Encoder design. Applied stimulus and add checkers from vectors generated by x264 reference software. From January 2013 to August 2015 (2 years 8 months) ASIC Verification Consultant @ Completed light weight verification infrastructure from scratch using System Verilog for the Layer 2 and 3 processing engine of a Router ASIC used in the linecard of the next generation Nexus 7000 platform and build Module level environments in System-Verilog for three IPs. From January 2013 to August 2014 (1 year 8 months)
Master’s Degree, Software Engineering @ International Technological University From 2014 to 2016 Master’s Degree, VLSI design @ University of Southern California From 2010 to 2012 Bachelor’s Degree, Electrical, Electronics and Communications Engineering @ Wuhan University From 2006 to 2010 Chong Yao is skilled in: Python, SQL, Java, Linux Operation System, Hadoop, JavaScript, Apache Spark, Scala, NumPy, R, Cassandra, Scikit-learn, HTML5, Twitter Bootstrap, jQuery
Websites:
https://chongyaorobin.wordpress.com/
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