Senior hardware engineer at Oracle. I am a circuit engineer designing static random access memory (SRAM) and custom circuits for Oracles' leading edge SPARC microprocessor. My responsibilities include: (1) design the high-speed, high-performance and low-power SRAM blocks such as register files, caches, and CAMs for next generation SPARC processor (2) investigate the possible improvements for SRAM memory...
Senior hardware engineer at Oracle. I am a circuit engineer designing static random access memory (SRAM) and custom circuits for Oracles' leading edge SPARC microprocessor. My responsibilities include: (1) design the high-speed, high-performance and low-power SRAM blocks such as register files, caches, and CAMs for next generation SPARC processor (2) investigate the possible improvements for SRAM memory architecture and circuitry such as novel sensing schemes, read/write assistance, and process-tolerance circuits to ensure its functionality and reliability at cutting-edge nanotechnology nodes (3) study and finalize the SRAM block design by enhancing the back-end analysis accuracies and precisionsSenior Hardware Engineer @ From August 2013 to Present (2 years 5 months) Ph.D Student @ Ph.D Candidate at Prof. Philip Wong’s Research Group (http://nano.stanford.edu/). Ph. D thesis project includes:  Investigating the film properties of atomic-layer deposited Al2O3, HfO2 and their possibility to use as the resistive switching materials as well as the potential innovations to the resistance random-access memory (RRAM) structures.  Integration of CNT with RRAM: combine carbon nanotubes (CNT) with RRAM memory cells to achieve ultra-small memory active area and cross-bar memory array. From January 2009 to August 2013 (4 years 8 months) Summer intern as device engineer @ Ground rule validation infrastructure setup using statistical analysis tool SAS at 28G bluk CMOS device team. Project involves SAS programing and ground rule fail/pass mechanism analysis and comparison of different criteria. From June 2011 to September 2011 (4 months) Summer intern @  Investigating the possible memory material combinations to achieve low switching current in RRAM devices as well as reducing the operation energy consumption.  Study the resistance switching bias polarity dependence of RRAM with electrode materials From June 2010 to September 2010 (4 months) TaiwanPh.D, Electrical Engineering @ Stanford University From 2010 to 2013 M.S., Electrical Engineering @ Stanford University From 2008 to 2010 B.S., Microelectronics @ Peking University From 2004 to 2008 Yi Wu is skilled in: SPICE, Matlab, Labview, Cadence, ALD, SAS, Agilent ADS, E-beam Evaporation, Semiconductors, Simulations, Verilog, Characterization, Nanotechnology, Cadence Virtuoso, Thin Films, Nanofabrication, Physics
Senior Hardware Engineer
August 2013 to Present
January 2009 to August 2013
Summer intern as device engineer
June 2011 to September 2011
Industrial Technology Research Institution (ITRI), Taiwan
June 2010 to September 2010
What company does Yi Wu work for?
Yi Wu works for Oracle
What is Yi Wu's role at Oracle?
Yi Wu is Senior Hardware Engineer
What industry does Yi Wu work in?
Yi Wu works in the Internet industry.
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