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Yazdan Torabian

Senior FPGA design engineer

Senior FPGA Design Engineer │ Senior ASIC Design Engineer │ Deep Analytical, Architecture and Programming Exp │MS Degree

San Jose, California

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Yazdan Torabian's Email Addresses & Phone Numbers

Yazdan Torabian's Work Experience

Tektronix

Senior FPGA design engineer

October 2018 to January 2019

San Francisco Bay Area

General Dynamics Mission Systems

Senior FPGA Design Engineer

February 2017 to May 2017

Bloomington, MN

mCube, Inc.

FPGA Design Engineer

November 2016 to January 2017

San Jose, CA

Yazdan Torabian's Education

Santa Clara University

Certificate, Digital Signal Processing

2012 to 2015

San Jose State University

Master’s Degree, Electrical Engineering

2004 to 2007

Georgia Institute of Technology

Bachelor’s Degree, Computer Engineering

1996 to 1999

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Yazdan Torabian's Estimated Salary Range

About Yazdan Torabian's Current Company

Tektronix

Frequently Asked Questions about Yazdan Torabian

What company does Yazdan Torabian work for?

Yazdan Torabian works for Tektronix


What is Yazdan Torabian's role at Tektronix?

Yazdan Torabian is Senior FPGA design engineer


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Yazdan Torabian's personal email addresses are y****[email protected], and y****[email protected]


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Yazdan Torabian's business email addresses are not available


What is Yazdan Torabian's Phone Number?

Yazdan Torabian's phone (213) ***-*294


What industry does Yazdan Torabian work in?

Yazdan Torabian works in the Computer Hardware industry.


About Yazdan Torabian

📖 Summary

Senior FPGA design engineer @ Tektronix From October 2018 to January 2019 (4 months) San Francisco Bay AreaSenior FPGA Design Engineer @ General Dynamics Mission Systems ►Provided FPGA design and development expertise for digital logic design projects targeting FPGA solutions within a military environment. Collaborated and executed within a team environment, achieving and integrating multiple design solutions. Completed FPGA Digital Logic Design, Synthesis, Timing Analysis, Verification, and lab integration activities. Achieved all deliverables and expectations for contracted projects.- - - - - - - - - - - - - - - - - - - - EXCELLENCE IN PERFORMANCE - - - - - - - - - - - - - - - - - - - -➪ Developed within the PCI_E DMA engine using Xilinx Vivado, ChipScope, and Xilinx PCIE UltraScale Kintex 7 Core.➪ Designed a DMA Descriptor Tracker, similar to a Contents Addressable Memory (CAM), to track different Descriptors that are coming to the FPGA.➪ Designed an On-chip Analyzer for storing up to 512 unique DMA Descriptors. From February 2017 to May 2017 (4 months) Bloomington, MNFPGA Design Engineer @ mCube, Inc. ►Recruited to fill a critical 3-month contract position, for the development, design, test, validation, and debugging within a semiconductor environment.On a daily basis, worked with Code-Scape Jtag Debugger from Imagination Technology for debugging Embedded Mips Processor. Contributed to C Driver debug for I2C, UArt, and others. Achieved all deliverables for contracted project on time or ahead of expected delivery schedule. - - - - - - - - - - - - - - - - - - - - EXCELLENCE IN PERFORMANCE - - - - - - - - - - - - - - - - - - - -➪ Designed a FIFO Queue mechanism with Verilog for viewing and filtering AHB Bus transactions from the Mips Processor in the FPGA.➪ Designed several Verilog Monitor modules targeted toward Artix FPGA, including an AHB Bus, and an I2C monitor. From November 2016 to January 2017 (3 months) San Jose, CAFPGA Application / Design Engineer @ Achronix Semiconductor Corporation ►Served as FPGA subject matter expert on the Application Team and System Engineering Team. Implemented different protocols in the FPGA. Projects included Porting of Ethernet Hard IP, and Soft IP from one platform to another; Ethernet PCS programming; FPGA placement and timing closure constraints, and build of the Hard IP in the FPGA tool flows. BER design in the FPGA included PRBS-7, and PRBS-31 full BER detector design with programmable resolution of (10^-5 to 10^-12) targeted for Achronix FPGA. Performed SerDes Validation and Characterization; and Tests such as Jitter tolerance (Jtol), Transmitter equalization (FIR Filter Coefficients manipulation), Receive equalization, Clock Data Recovery Jitter tolerance, and PLL transfer functions.- - - - - - - - - - - - - - - - - - - - EXCELLENCE IN PERFORMANCE - - - - - - - - - - - - - - - - - - - -➪ Selected to join the System Engineering team to locate and resolve the SerDes corruption bug, which was causing data corruption. Resolved corruption bug issue, restored systems and achieved complete success. From July 2014 to January 2016 (1 year 7 months) Santa Clara, CASenior FPGA / Logic Design Engineer @ JDSU ►Served as Senior FPGA Engineer for the On-chip Logic Analyzer Project. Designed an On-chip Logic Analyzer similar to Xilinx Chip-Scope or Altera Signal Tap; different Triggering and Masking Capabilities. Implemented different protocols in the FPGA. Designed several board schematics with OrCad Capture. Provided expertise with different concepts of SAS/SATA protocol for FPGA implementations with Verilog/VHDL such as Out of Band Signaling, Speed-Negotiation windows, Optical OOB, HOLD/HOLA, 8B/10B encoder/decoder, Comma Detection and Alignment, Parallel LFSR implementation for Scrambler and CRC, and transmitter training.- - - - - - - - - - - - - - - - - - - - EXCELLENCE IN PERFORMANCE - - - - - - - - - - - - - - - - - - - -➪ Selected to resolve a critical bug in the SAS Jammer product being used by Facebook, which their internal IT department was unable to remedy. Resolved this critical issue, achieving complete client satisfaction. From June 2013 to June 2014 (1 year 1 month) Milpitas, CaliforniaSerDes Validation Engineer @ Xilinx Performed SerDes Validation and Characterization. Conducted tests such as Jitter tolerance (Jtol), Transmitter equalization (FIR Filter Coefficients manipulation), Receive equalization, Clock Data Recovery Jitter tolerance, and PLL transfer functions. - - - - - - - - - - - - - - - - - - - - EXCELLENCE IN PERFORMANCE - - - - - - - - - - - - - - - - - - - -➪ Completed characterization of GTH SERDES towards PCIE application. From October 2012 to May 2013 (8 months) San Jose, CaliforniaASIC to FPGA Emulation Engineer @ Quantenna Communications Performed a full range of ASIC design SOC emulations in to the FPGA for Software Validation purposes.- - - - - - - - - - - - - - - - - - - - EXCELLENCE IN PERFORMANCE - - - - - - - - - - - - - - - - - - - -➪ Selected to upgrade all the FPGA tools and products, and successfully achieved each initiative. From February 2012 to October 2012 (9 months) Fremont, CaliforniaSenior FPGA design engineer @ Northrop Grumman From January 2019 to November 2020 (1 year 11 months) Greater Los Angeles AreaSenior FPGA Design Engineer @ Eagle Seven ►Recruited as a subject matter expert (SME) in FPGA design and development for high frequency, low latency electronic financial trading systems. Provided hardware/software expertise across projects to include design lifecycle sub-processes, technical specifications, and architecture strategies; research and implementation of advanced concepts and technologies; and creating and executing test plans for design validation. Collaborated with members of the hardware engineering team to achieve best-in-class technical and intellectual solutions.- - - - - - - - - - - - - - - - - - - - EXCELLENCE IN PERFORMANCE - - - - - - - - - - - - - - - - - - - -➪ Designed a fully operational TCP/IP offload engine; a FIX 4.2 parser; and a UDP packet parser with Verilog.➪ Utilized Xilinx DMA Controller IP cores for transferring packets from FPGA to System memory.➪ Designed a fully operational message generator for CME financial exchange targeted for Altera FPGAs.➪ Designed a TCP checksum calculation module.➪ Designed a state machine for heart beating with CME server.➪ Designed a content addressable memory (CAM) based design for packet classification. From July 2017 to September 2018 (1 year 3 months) Greater Chicago AreaFPGA Storage Design Engineer @ Advantest ►Selected for the Firmware design protocol test group. Enhanced the FPGA design for Serial Attached SCSI (SAS) for 12 gig, 6 gig, and 3 gig line of products. Further developed FPGA design targeted towards transmitter training, SNW-1, and SNW-2. Extensively used Lecroy analyzer for SAS protocols, and Xilinx ChipScope for Xilinx Virtex-7 FPGA. Achieved all deliverables for contracted project. - - - - - - - - - - - - - - - - - - - - EXCELLENCE IN PERFORMANCE - - - - - - - - - - - - - - - - - - - -➪ Leveraged deep analytical skills to identify a timing issue within the Advantest SAS SNW-2 window, and validated resolution of bug. From June 2016 to September 2016 (4 months) Santa Clara, CASenior FPGA / Logic Design Engineer @ LeCroy Corporation Signal processing implementation in the FPGA and implementation of different Protocols. Worked on different concepts of SAS/SATA protocol for FPGA implementations with Verilog/VHDL, such as Out of Band Signaling, Speed-Negotiation windows, Optical OOB, HOLD/HOLA, 8B/10B encoder/decoder, Comma Detection and Alignment, Parallel LFSR implementation for Scrambler and CRC, and transmitter training. - - - - - - - - - - - - - - - - - - - - EXCELLENCE IN PERFORMANCE - - - - - - - - - - - - - - - - - - - -➪ Designed the SAS/SATA error injector which was highly anticipated and was sold into the market. ➪ Designed a DDS (Direct Digital Synthesis) system in the FPGA for the function generator project for generating signals such as sine, cosine. From June 2004 to October 2011 (7 years 5 months) Santa Clara, CaliforniaDigital Board Design Engineer @ Alcatel-NeoScale - - - - - - - - - - - - - - - - - - - EXCELLENCE IN PERFORMANCE - - - - - - - - - - - - - - - - - - - -➱ Designed several Board Schematics, including Dual CT3 Carrier Board for Alcatel.➱ Designed a USB 3.0 Board Schematic for Lecroy.➱ Familiar with Circuit Concepts in Board Design, including Crosstalk, Return Current Path, and Decoupling Capacitors. From 2000 to 2004 (4 years) Milpitas, CA


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In a nutshell

Yazdan Torabian's Personality Type

Introversion (I), Intuition (N), Thinking (T), Judging (J)

Average Tenure

1 year(s), 7 month(s)

Yazdan Torabian's Willingness to Change Jobs

Unlikely

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