Digital design engineer with experience in design, development and deployment of IP solutions and systems targeted towards FPGAs with core competencies in the following areas • Micro-architecture and RTL design of multi-clock domain, high speed digital logic • Design and application of PCI Express IP & Solutions (End-Point, RootPort and Switches) • Design experience with Xilinx FPGA’s - IP cores, AXI4 Protocol and MicroBlaze Processor • Xilinx Vivado and ISE toolset expertise with proficiency in floor-planning and timing closure • Hardware Validation and Prototyping on FPGA platforms • Hardware bring-up and debug skills with expertise in using scopes and analyzers • Verification and test bench creation with use of randomization, assertions, and coverage • Board design experience including schematic capture, layout and DVT • SW driver integration and scripting with Tcl & python • Team contributor with proven mentoring and leadership abilities • Proven track record for successful, high quality product delivery

Senior IP Design Engineer @ From March 2012 to Present (3 years 10 months) MTS-2 HW Engineer @ From September 2008 to April 2012 (3 years 8 months) MTS-1 HW Engineer @ From January 2008 to August 2008 (8 months) Graduate Teaching Assistant @ From January 2007 to December 2007 (1 year) Lab Administrator Trainee @ From October 2006 to December 2007 (1 year 3 months) Intern @ From May 2007 to July 2007 (3 months) Bengaluru Area, India

MS, Computer Engineering @ Villanova University From 2006 to 2008 Bachelor of Engineering, Electronics and Communication @ Visvesvaraya Technological University From 2002 to 2006 Vivek Surabhi is skilled in: FPGA, ModelSim, Xilinx, VHDL, SR-IOV, PCIe, Verilog, NCSim, ClearCase, Logic Analyzer, RTL coding, Timing Closure, NC-Verilog, Floorplanning, Power Analysis