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Vivek Surabhi

Senior IP Design Engineer @ Xilinx

Vivek Surabhi Contact Details

Location:
Santa Clara, California
Work:
Senior IP Design Engineer @ Xilinx
MTS-2 HW Engineer @ Hughes Network Systems
MTS-1 HW Engineer @ Hughes Network Systems
Education:
Bachelor of Engineering, Electronics and Communication @ Visvesvaraya Technological University
About:

Digital design engineer with experience in design, development and deployment of IP solutions and systems targeted towards FPGAs with core competencies in the following areas • Micro-architecture and RTL design of multi-clock domain, high speed digital logic • Design and application of PCI Express IP & Solutions (End-Point, RootPort and Switches) • Design experience with Xilinx FPGA’s 

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