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Vishal Gala Contact Details

Austin, Texas, United States
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Senior ASIC Design/Verification Engineer @ Working with the DDR Memory Controller team. Responsible for Verification of sub-block of memory controller. Developed constrained random tests to meet coverage goals. Developed cycle accurate System Verilog models. Developing drivers in C for Post silicon bring up,validation and debug of the sub-block. Debugging issues using Jtag,Logic Analyzer, Oscilloscope and implementing software 

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