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Vincent Kan

Staff Design Verification Engineer @ Xilinx

Vincent Kan Contact Details

Location:
San Francisco Bay Area
Work:
Staff Design Verification Engineer @ Xilinx
Design Engineer, MTS - Full-Chip and System Verification @ Altera
Design Engineer - USB Products @ Atmel
Education:
Bachelor of Applied Science, Computer Engineering @ The University of British Columbia
About:

Staff Design Verification Engineer @ • System and block level verification for SerDes PMA and PCS with OVM From August 2012 to Present (3 years 5 months) San Francisco Bay AreaDesign Engineer, MTS - Full-Chip and System Verification @ • Full-chip verification for Altera's first ARM-based SoC FPGA (28nm). • Defined full-chip configuration test plan for ARM-based 

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