Subeer Rangra's Email & Phone - Université de Technologie de Compiègne

Subeer Rangra's Work Experience

Université de Technologie de Compiègne

PHD Researcher

September 2014 to Present

Ansaldo STS

Intern

January 2014 to July 2014

PragmaDev

Intern

May 2013 to August 2013

Paris Area, France

Subeer Rangra's Education

Ecole supérieure d'Ingénieurs en Electrotechnique et Electronique

Master's degree Computer Engineering

2012 to 2014

B K Birla Institute of Engineering & Technology

Bachelor of Technology Computer Science

2008 to 2012

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About Subeer Rangra's Current Company

Université de Technologie de Compiègne

Thesis title: A Systems-of-Systems approach for modeling and integrating human factors in risk analysis: Application to advanced driver assistance systems (ADAS) and railway systems at HEUDIASYC laboratory (UMR CNRS 7253) at UTC.

Frequently Asked Questions about Subeer Rangra

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Subeer Rangra works for Université de Technologie de Compiègne

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Subeer Rangra is PHD Researcher

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Subeer Rangra's personal email addresses are and s[email protected] and s[email protected]

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Subeer Rangra's phone () * *** 285

What industry does Subeer Rangra work in?

Subeer Rangra works in the Computer Software industry.

About Subeer Rangra

📖 Summary

I am currently (August 2015) a PhD researcher at the Université de Technologie de Compiègne. My thesis is to work towards risk analysis of the human factors (Human Reliability Analysis) in the transportation domain, in particular railway (ERTMS) and automotive (ADAS) domain. My research interests include safety critical systems, human factors, risk analysis and system of systems among others. EDIT: More updates on my website https://www.hds.utc.fr/~rangrasuPHD Researcher @ Thesis title: A Systems-of-Systems approach for modeling and integrating human factors in risk analysis: Application to advanced driver assistance systems (ADAS) and railway systems at HEUDIASYC laboratory (UMR CNRS 7253) at UTC. From September 2014 to Present (1 year 4 months) Intern @ This internship aims to establish formal verification in the software development of railway signalling systems conforming to the standards of ERTMS (European Rail Traffic Management System) signalling system (RBC and interlocking in particular). Following the recommendations of the CENELEC EN 50128 railway standard, there is a need to incorporate formal methods for the verification and validation of a SIL level 4 software system. The objectives achieved during this internship included • A thorough analysis of the existing application of formal methods in development and or verification in the domain of domain railway signaling and similar systems. • Analysis of feedback from CBTC regarding the usage of induction based SMT solvers. • Use of synchronous programming language (SCADE/Lustre) for formal specification of safety requirements. • Use of automatic test case generator tool GATeL (CEA-LIST) to complement formal verification. • Establishing a subset of evidence based on data from a real industrial project. From January 2014 to July 2014 (7 months) Intern @ Enable the export and verification of SDL models using the pivot language Fiacre. This project is experiments the Fiacre/Tina tool chain for the verification of SDL descriptions. An experimental version of RTDS allows one to translate SDL descriptions into Fiacre descriptions. These Fiacre descriptions, augmented with properties declarations and verification requests, are then model checked using the Tina tools. Paper published in the Proceedings of the European conference ERTMS 2014. From May 2013 to August 2013 (4 months) Paris Area, FranceInternship @ This was the project undertaken by me in CEERI, Pilani as part of the mandatory industrial training cum experience. A Basic study of VHDL was done and in the same language the implementation of CORDIC Algorithm was carried out. From June 2011 to July 2011 (2 months) Internship @ My Internship at ECE in Paris involved the interconnection of two Contiki based Operating Systems via a USB link. Transfer of a string of data was implemented and a basic study of 6LowPAN was also carried out. From January 2011 to March 2011 (3 months) Paris Area, FranceMaster's degree, Computer Engineering @ Ecole supérieure d'Ingénieurs en Electrotechnique et Electronique From 2012 to 2014 Bachelor of Technology, Computer Science @ B K Birla Institute of Engineering & Technology From 2008 to 2012 Subeer Rangra is skilled in: C++, C, Java, C#, Linux, HTML, Microsoft Office, Operating Systems, VHDL, PL/SQL, Image Processing, Computer Science, Computer Vision, Programming, Algorithms

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