Image of Simon Chaput

Simon Chaput

Ph.D. Candidate @ Harvard School of Engineering and Applied Sciences

Founder & President at Boréas Technologies

Bromont, Quebec, Canada

Ranked #1,093 out of 21,860 for Ph.D. Candidate in United States

Section title

Simon Chaput's Email Addresses & Phone Numbers

Simon Chaput's Work Experience

Harvard School of Engineering and Applied Sciences

Ph.D. Candidate

September 2013 to Present

Greater Boston Area

Teledyne DALSA

IC Designer

May 2011 to June 2013

Bromont, Quebec, Canada

MDA

Electrical Engineer Intern

January 2011 to April 2011

Simon Chaput's Education

Harvard University

Doctor of Philosophy (Ph.D.) Integrated Circuit Design

2013 to 2018

Massachusetts Institute of Technology

Electrical Engineering

2013 to 2014

Université de Sherbrooke

M. Sc. A Electrical Engineering

2011 to 2013

Simon Chaput's Professional Skills Radar Chart

Based on our findings, Simon Chaput is ...

Purposeful
Self-reliant
Analytical

What's on Simon Chaput's mind?

Based on our findings, Simon Chaput is ...

56% Left Brained
44% Right Brained

Simon Chaput's Estimated Salary Range

About Simon Chaput's Current Company

Harvard School of Engineering and Applied Sciences

Design of the analog front end of a custom SoC in a 40 nm CMOS process. The analog front end includes: -Multichannel SAR ADC -Bandgap voltage reference -Low-dropout regulator (LDO) -Charge pump -Operational Amplifiers

Frequently Asked Questions about Simon Chaput

What company does Simon Chaput work for?

Simon Chaput works for Harvard School of Engineering and Applied Sciences


What is Simon Chaput's role at Harvard School of Engineering and Applied Sciences?

Simon Chaput is Ph.D. Candidate


What is Simon Chaput's personal email address?

Simon Chaput's personal email address is si****[email protected]


What is Simon Chaput's business email address?

Simon Chaput's business email address is s****[email protected]


What is Simon Chaput's Phone Number?

Simon Chaput's phone (416) ***-*342


What industry does Simon Chaput work in?

Simon Chaput works in the Semiconductors industry.


About Simon Chaput

📖 Summary

I am a strongly motivated analog and mixed-signal IC designer constantly pushing design boundaries to achieve better performances. My experience includes industry and academic ASIC design in high voltage (up to 300 V) and deep submicron (40 nm) processes.Ph.D. Candidate @ Design of the analog front end of a custom SoC in a 40 nm CMOS process. The analog front end includes: -Multichannel SAR ADC -Bandgap voltage reference -Low-dropout regulator (LDO) -Charge pump -Operational Amplifiers From September 2013 to Present (2 years 2 months) Greater Boston AreaIC Designer @ Design and layout of power management IC in a high voltage BCD process. Designs included the following functional blocks: - Bandgap voltage reference, - Low dropout regulator (LDO), - Charge pump, - Comparators, - Operational Amplifiers, - Power devices. Select IC package Design test PCB Characterize and model power devices Test and debug silicon at wafer level and package level From May 2011 to June 2013 (2 years 2 months) Bromont, Quebec, CanadaElectrical Engineer Intern @ Perform worst-case analysis on communication buses Build communication bus prototype for lab measurement Research communication bus models in the literature From January 2011 to April 2011 (4 months) Electrical Engineer Intern @ In Design & Innovation department: -Program, analyze and debug new and legacy software (C, Assembly language) -Program LCD screen driver -Diagnose embedded system failures -Write requirements and documentation for new products -Write and execute test plans From January 2010 to April 2010 (4 months) Electrical Engineer Intern @ In Design & Innovation department: -Program, analyze and debug new and legacy software (C, Assembly language) -Propose improvements to actual electrical schematics -Search information on new technologies that could be integrated in next generation product -Write and execute test plans From January 2009 to April 2009 (4 months) Electrical Engineer Intern @ In the Test Facilities Engineering department: -Write a five-year technology plan to guide the integration of new technologies in company’s test cells. This involved gathering information on test cells technology needs from many users in different plants; arranging meetings for managers and unionized workers; analyzing the information to establish priorities and presenting the plan to various staff groups to obtain their input and consent. -Develop Excel tools to facilitate analysis of the information -Make an inventory of equipment in all test cells and develop a tool to improve productivity of engineers and technicians. From May 2008 to August 2008 (4 months) Doctor of Philosophy (Ph.D.), Integrated Circuit Design @ Harvard University From 2013 to 2018 Electrical Engineering @ Massachusetts Institute of Technology From 2013 to 2014 M. Sc. A, Electrical Engineering @ Université de Sherbrooke From 2011 to 2013 Power Manadgement IC @ MEAD Education From 2012 to 2012 B. Eng., Electrical Engineering @ Université de Sherbrooke From 2007 to 2011 Electrical Engineering @ University of Utah From 2010 to 2010 Simon Chaput is skilled in: Analog Circuit Design, Integrated Circuit..., Power Electronics, Mixed Signal, Power Management, FPGA, PCB design, Embedded Systems, Matlab, Electrical Engineering, Power Devices, IC layout, PSIM, Cadence, Cadence Analog Artist, Testing, Simulations, Cadence Spectre, Microcontrollers, Cadence Virtuoso, VHDL, Verilog, IC, C, ASIC, CMOS, Analog, Microelectronics, SoC, PCB Design, Electronics, C++, Semiconductors


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In a nutshell

Simon Chaput's Personality Type

Introversion (I), Intuition (N), Thinking (T), Judging (J)

Average Tenure

0 year(s), 11 month(s)

Simon Chaput's Willingness to Change Jobs

Unlikely

Likely

Open to opportunity?

There's 90% chance that Simon Chaput is seeking for new opportunities

Simon Chaput's Achievements

Harvard Graduate Fellowship

Issued by Harvard University · September 2013

Doctoral Research Scholarship

Issued by Fonds de recherche Nature et technologies Québec (FQRNT) · September 2013

Famille Louis Lagassé scholarship

Issued by Université de Sherbrooke Foundation · November 2012

Léonard de Vinci Medal

Issued by Université de Sherbrooke · November 2011

BMP Innovation scholarship

Issued by NSERC, FQRNT · 2011

Dean's list - College of Engineering

Issued by University of Utah · 2010

Rio Tinto Fer et Titane

Issued by Université de Sherbrooke Foundation · November 2010

J.A. Bombardier scholarship

Issued by Université de Sherbrooke Foundation · November 2009

Additional Honors & Awards

Issued by - · -

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