Sergey Dubinin’s Email & Phone

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Sergey Dubinin

Digital Verification and Design Engineer (UVM / SystemVerilog / Verilog) @ NXP Semiconductors

Sergey Dubinin Contact Details

Gratkorn, Styria, Austria
Digital Verification and Design Engineer (UVM / SystemVerilog / Verilog) @ NXP Semiconductors
FPGA Verification / Design Engineer (Contractor for short-term project) @ Opgal
FPGA Design Engineer (Contractor for short-term project) @ Elisra
@ Cadence

Experienced and highly motivated Digital Design and Verification Engineer with strong dedication and interest to the following areas: ♦ Functional Verification with SystemVerilog based on cutting-edge reusable UVM methodology ♦ Digital Design (mostly with Verilog) Successfully implemented from scratch a couple of FPGA/ASIC projects (partly listed below) covering all Front-End stages (MRD -> Spec/Test plan documentation -> 

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