Electrical Design Engineer with a broad background in hardware and software including test, modeling, characterization, layout, and circuit design. Proven leadership in both analog and digital circuit design, design methodology, design flow integration, and automation.

Staff Verification Engineer @ Design verification for advanced optical sensors and sensor interfaces. From March 2015 to Present (8 months) Plano, TXProduct Engineer @ Managed the test chip design, assembly, and characterization testing of high speed IOs. From September 2010 to March 2015 (4 years 7 months) Plano, TXProgrammer Analyst (Contractor) @ Software coding for formatting client data for laser printing and mailing. From July 2010 to September 2010 (3 months) Carrollton, TXMGTS - Electrical Design Engineer @ ASIC PLL Design Group Validated, integrated, and released custom IP in leading technologies. Provided PLL application support, generated models, developed test benches, and evaluated IP in lab. Evaluated 3rd party IP and integrated into design flow. * Improved PLL verilog models providing self-checking of use outside of specified range and start-up sequence. * Provided PLL peer reviews to check physical implementation, test access, and compliance to specifications, eliminating design re-spins. * Collected lab data to provide proof of concept feasibility to win three high profile designs. * Minimized customer PLL design issues by verifying every ASIC PLL prior to release for TI's 6-sigma quality for on-time delivery. * Created serial test interface blocks for PLLs in order to bypass customer logic during production testing and reducing number of interface pins for testchips. From January 2002 to January 2009 (7 years 1 month) Electrical Design Engineer @ ASIC Circuit Design Methodology Group Defined custom IP create methodology process. Drove quality and integration improvements. Expanded designers' productivity through automation of tasks and training on process flow. Supervised co-op students. * Applied methodology to PLL development comparing spice results to simulation patterns, eliminating functional discrepancies. * Authored checker control and capture tools gaining design wins after demonstration to customers. * Increased designers' productivity by generating multiple self-teaching labs on IP-create process. * Automated CM release process saving 5 staff days per month. * Mentoring of co-ops lead to three becoming full-time contributors after graduating. From January 1998 to January 2002 (4 years 1 month) Test Development Engineer @ ASIC Test Development Group Defined DFT flow, test flow, and test pattern generation flow. Introduced new 3rd party tools. Acted as interface between test engineers and design engineers. * Generated first ASIC Sunrise ATPG library increasing the use of ATPG in test. * Created a CGI interface script to decode taxonomy code, allowing designers to check cell properties, reducing the number of library re-spins. * Established key-value property system replacing taxonomy code saving 3 days per cell delivery. * Developed and taught world-wide training classes for TDL and various other internal TI ASIC flow tools which lead to 1 to 2 week cycle-time improvements. From November 1995 to January 1998 (2 years 3 months) Engineer @ Semi-custom design and layout of 8-bit microcontroller circuitry, Lab evaluation and characterization. From 1992 to 1995 (3 years) Design Engineer @ 8-bit microcontroller design group Designed 8-bit microcontroller circuitry including ALU, data path, clock, and I/O blocks. Evaluated and characterized microcontroller designs using lab equipment. Generated test programs and operated tester. From 1992 to 1995 (3 years)

BSEE, Semi-Conductor Design @ North Carolina State University From 1987 to 1992 Scott Williams is skilled in: Physical Design, Semiconductors, ASIC, Mixed Signal, Static Timing Analysis, Circuit Design, Analog, IC, FPGA, Hardware Architecture, DFT, EDA, RTL design, TCL, Signal Integrity, VLSI, Timing Closure, Debugging, Cadence, Semiconductor Industry, Test Engineering, Verilog