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Santosh Mundhe

Sr Engineer

Design Verification Engineer at Microsoft

United States

Section title

Santosh Mundhe's Email Addresses & Phone Numbers

Santosh Mundhe's Work Experience

Cavium Inc

Sr Engineer

December 2016 to July 2018

San Jose


Design Verification Engineer

sunnyvale california

Marvell Semiconductor

Senior Verification Engineer

July 2018 to August 2019

Santa clara california

Santosh Mundhe's Education

University of Southern California

MS, Electrical Engineering

2008 to 2010

Savitribai Phule Pune University

Bachelor’s Degree, Electrical, Electronics and Communications Engineering

2002 to 2006

About Santosh Mundhe's Current Company

Cavium Inc

About Santosh Mundhe

📖 Summary

Sr Engineer @ Cavium Inc From December 2016 to July 2018 (1 year 8 months) San JoseDesign Verification Engineer @ Microsoft sunnyvale californiaSenior Verification Engineer @ Marvell Semiconductor From July 2018 to August 2019 (1 year 2 months) Santa clara californiaStaff II Verification Engineer @ Broadcom ● Developed a UVM environment to extensively verify the glue logic around SATA, UART, I2C, RTCcomprising of AHCI driver, Test sequences, UVM register adapters, Device VIP’s, Scoreboard.● Functional and code coverage was analyzed for block closure.● Performed Gate level simulation for SATA, UART, I2C RTC controllers with TT and SS corners .Full Chip Testing (UVM, Systemverilog, C, Assembly, Perl)● Responsible for full chip level testbench development for basic access to SATA controller, UART, I2C,NAND, NOR, SPI controller block for ARM V8 32 core server processor.● Conducted Directed tests to verify DMA, NCQ transactions for SATA controllers at full chip level.● Verified Arbitration logic for I2C, Nor controllers between M3 and V8 processor at full chip level.● Created System level tests (device disable, device reset, pll frequency change) for PCIE, SATA, UART,I2C, NAND, NOR, SPI controller.● Assisted in bring up of SATA controller using AHCI Host Speed Bridge on Palladium.Post Silicon Validation ( Lecroy Analyzer for SATA, Totalphase I2C analyzer)● Successful loading of AHCI driver for SATA controller with help of LeCroy analyzer.● Devised Test strategy and test plans and executed the same for I2C controller with the help ofTotalphase I2C analyzer. From January 2014 to December 2016 (3 years) Santa ClaraDesign Verification Engineer @ Marvell Semiconductor ● Lead a team that was responsible for SOC level verification for flash controller (RTL and GATE).● Devised Testing Strategy and implemented plans, test scenarios to execute the logic verification flow ofASIC development cycle for flash controller.● Responsible for functional and code coverage and running regressions. From June 2011 to December 2013 (2 years 7 months) Santa ClaraAsic Design Intern @ Sigma Designs ● Assisted in DRC reporting and cleaning, LVS debugging at full chip (55nm) using Calibre DRC/LVS aswell as Quartz DRC.● Generating GDSII cut for IP review using calibre rve.● Created and maintain all the IP collateral and golden files for full chip place and route. From September 2010 to June 2011 (10 months) Milpitas

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Frequently Asked Questions about Santosh Mundhe

What company does Santosh Mundhe work for?

Santosh Mundhe works for Cavium Inc

What is Santosh Mundhe's role at Cavium Inc?

Santosh Mundhe is Sr Engineer

What is Santosh Mundhe's personal email address?

Santosh Mundhe's personal email address is s****[email protected]

What is Santosh Mundhe's business email address?

Santosh Mundhe's business email addresses are not available

What is Santosh Mundhe's Phone Number?

Santosh Mundhe's phone (***) ***-*230

What industry does Santosh Mundhe work in?

Santosh Mundhe works in the Computer Hardware industry.

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Extraversion (E), Intuition (N), Feeling (F), Judging (J)

Average Tenure

1 year(s), 10 month(s)

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