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Rashmi Finavia

Senior Verification Engineer @ Intel

Rashmi Finavia Contact Details

Austin, Texas, United States
Senior Verification Engineer @ Intel
Advisory Physical Design Engineer @ IBM
Design Engineer @ NXP Semiconductors

Physical Design Engineer @ From August 2014 to Present (1 year 5 months) Design Verification Engineer @ From January 2006 to July 2014 (8 years 7 months)

Bachelor of Engineering (BSEE), VLSI @ UT Austin From 2002 to 2007 Rashmi Finavia is skilled in: FPGA, Labview, Matlab, C++, SystemVerilog, SoC, ASIC, Verilog, Functional Verification, RTL design, VLSI, Logic Design, PCIe, Static Timing Analysis, Specman

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