BE (EC), Electronics and Telecommunications @
Government Engineering College Aurangabad
Career spanning more than 16 years of extensive experience, with direct contributing, hands on roles in Architecture, Design and Implementation of ASIC/SoC, Video Codecs, reusable IP blocks, ASSP and FPGA based designs executed for several leading global semiconductor companies. Consistent track record of being to go person for handling complex projects, providing solutions, debugging and resolving complex
Career spanning more than 16 years of extensive experience, with direct contributing, hands on roles in Architecture, Design and Implementation of ASIC/SoC, Video Codecs, reusable IP blocks, ASSP and FPGA based designs executed for several leading global semiconductor companies. Consistent track record of being to go person for handling complex projects, providing solutions, debugging and resolving complex technical issues.
+ Image/Video Processing & Image/Video compression. H.264, MPEG, Graphics & Display processing
+ AMBA, ARM Primecell IP, ARM AMBA AHB, AXI protocols
+ USB2.0 and FireWire/1394
+ Low Power techniques. UPF based flow.
+ DDR3 Controller and PHY, SRAM, SSRAM, DMA Engine, Cache Controller
+ SOC Architecting, Integration
+ RapidIO [Multi-Processor Interconnect] standard
+ MIPI [Mobile Industry Processor Interface] Alliance standards.
* IP Design, Verification and Synthesis. Module level ASIC Design and Verification.
* Full System level SOC Integration, Block level and Chip Top level Synthesis, Verification and multi-mode STA [Static Timing Analysis] along with OCV, PVT analysis, timing and logical ECO, LEC, Lint, CDC.
* Track record of involvement in successful tape-out in various process technology nodes starting from 90nm, 65nm, 40nm, 22nm to most recent 14nm.
* Expertise in interaction with Physical Design team for successful ASIC tape-out. Understanding and analysis of Floorplan, Placement, Clock-Tree-Synthesis, global and detailed Routing.
FPGA based Design, Verification and Validation on Board
* Vast experience in working with customers, client teams across multiple geographies. Experienced in technically leading teams.
* Excellent organizational, communication, presentation and documentation skills.
* Experienced in requirements gathering, Proposal generation, SoW creation and closure.
Sr. VLSI Technical Consultant @ * System Architecture experience in developing architecture for product from specification. Proposed and developed ASIC SoC and FPGA based solutions.
* Developed Architecture solution for an Extreme performance H.264 real time QVGA Encoder system for a leading Japanese broadcaster to broadcast TV channels to mobile devices.
* Part of several successful tape-outs in various responsibilities such as Synthesis+DFT, JTAG + MBIST insertion, LEC, pre and Post-Layout sign-off STA, timing and logical ECO's in various process technology nodes starting from 90nm, 65nm, 40nm, 22nm to most recent 14nm for various gate counts starting from 3M to 55M.
* Vastly Experienced in IP development.
+ Involved as technical lead for Development of a full featured RapidIO Gen-2.2 IP core supporting x1, x2 and x4 lane modes, each lane capable of operating at 6.25GBaud.
+ Development of MIPI specified DSI and CSI PHY IP's which includes development of DFE and integration of AFE.
+ Developed multiple ARM AMBA AHB based Primecell IP including multiple flavors of complex Memory controllers and DMA controller.
* Image and Video processing domain solutions such as Pro-MPEG based system, display controllers, JPEG2000 IP.
* Mixed signal digital PHY block development.
+ For MoCA ASIC, Micro-architect and design critical blocks such as DC-Offset Estimation and Correction, I-Q Calibration and Correction, Numerically Controlled Oscillator based Tone Generator with amplitude control, Gain Extraction and Control for LNA, PA, LPF, Mixer, Squarer etc.
+ For MIPI IP's, design and development of resistor compensation block,
* Strong experience in performing top level and sub-system level RTL integration.
+ Ownership of 1.8Million gate sub-system consisting of 800MHz/1600MHz DDR3 Controller IP + PHY Hard Macro sub-system. Design of additional features such as design of Overlapped Data protection for DDR3 data bus and address protection schemes. From 1999 to Present (16 years) Specialist @ Sr. VLSI Technical Consultant From February 2004 to Present (11 years 11 months) Sr. Project Associate @ From March 1995 to September 1997 (2 years 7 months)
MS, Microelectronics, 8.4/10 @ Indian Institute of Technology, Madras From 1996 to 1999 BE (EC), Electronics and Telecommunications @ Government Engineering College AurangabadHSC, electronics physics @ maulana azad college Rajesh Rajaram is skilled in: ASIC, SoC, VLSI, FPGA, Verilog, ARM, Embedded Systems, System Architecture, Debugging, Electronics, Architecture, Microelectronics, Architectures, Functional Verification, Static Timing Analysis
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