US Citizen, Ph.D. candidate in Electrical and Computer Engineering, Electronic Design Automation Software Engineer, with 4+ years Industrial Work Experience in Raytheon IDS, a startup System Validation Software Solution Company and in a Leading Supplier of FPGA Synthesis Software Company, 5+ years Academic Experience in Digital Fault Tolerance and Testability, using Cutting Edge Technologies, with 14 Published Papers in Prominent Conferences, and Skilled Digital Hardware Design and Verification Engineer with total of 5+ years Work Experience in Digital FPGA and ASIC Design, Development, Simulation, Synthesis, Emulation, Verification and Test, using Current Tools and Technologies. Specialties:■ Behavioral/RTL Modeling, Design, Implementation, Verification, Synthesis, Simulation, and Test of Digital Systems. ■ HD(V)Ls such as Verilog, SystemVerilog, VHDL, and their PLIs such as VPI and VHPI, and also familiar with SystemC. ■ Verification Libraries and Methodologies such as QVL, OVL, and OVM/UVM. ■ C/C++, MS-VC++, Java, VB, Perl, Matlab, HTML, and Assembly Language.

Sr. Electrical Engineer II @ ■ Member of the Embedded Processors & FPGA Verification Section in the Power and Electronic Systems Department of the Electrical Design Directorate at Raytheon IDS Headquarter. ■ Raytheon Six Sigma Specialist in improving FPGA Verification Process. ■ Research and Feature Development of the FPGA Verification Environment for multiple Digital IO2E FPGA Designs (Interfacing Multiple IO Protocols to the Ethernet Backbone), using SystemVerilog and OVM. ■ Engineering Test Support at 100K Clean-Room Surface Acoustic Wave Module Lab. and Microwave Fab. ■ Bugs and Regression Failures Resolution and QoR Improvement in FPGA Verification Process. From May 2009 to Present (6 years 7 months) Software Engineer @ ■ Member of the Technology Team. ■ Research and Feature Development of the Carbon Model Studio’s (Cycle-Accurate Emulator) Interfacing and Accessing APIs, using C++. ■ Research and Feature Development of the internal Test-Driver Code Generator for Verilog and VHDL RTL Designs used for regression test process in both C++ (for Carbon Compiler) and Verilog/VHDL (for comparison), using C++. ■ Research and Feature Development of the XML Code Generator of the Design Hierarchy for Verilog and VHDL RTL Designs, using C++, used by Carbon Model Studio’s GUI Team. ■ Bugs and Regression Failures Resolution and QoR Improvement in Carbon Compiler and Model. From December 2007 to June 2008 (7 months) Synthesis Developer @ ■ Member of the Xilinx Mapper Team. ■ Research and Feature Development of the Synplify-Pro/-Premier’s Xilinx Mapper for Spartan-II, Spartan-III, Virtex-4, and Virtex-5 FPGA Families, including but not limited to Logic and Sequential Optimization and Block RAM Interfacing and Mapping, using C. ■ Collaborated closely with Timing Team on Synplify-Pro/-Premier’s Xilinx Mapper Timing Correlation, Forward Annotation, and Constraint Application, using C. ■ Research and Feature Development of the Synplify-Pro ValuePack’s Xilinx Mapper. ■ Research and Feature Development of the UCF2SDC and EDIF2SRS File Format Converters for Synplify-Pro/-Premier’s Xilinx Mapper, using C. ■ Creating Specification Documents for Synplify-Pro/-Premier’s Xilinx Mapper Developing Features. ■ Bugs and Regression Failures Resolution and QoR Improvement in Synplify-Pro/-Premier’s Xilinx Mapper. From October 2005 to November 2007 (2 years 2 months) Design Engineer @ ■ Summer Internship. ■ Design, Implementation, and Test of the Transducers’ Driver and Microphones’ Preamplifiers PCBs, Sampling and Triggering Software Codes for an Ultrasonic Motion Capture Environment using National Instruments LabVIEW, Altium Designer (Protel), PentaLogix ViewMate, National Instruments’ and Data Translations’ Data Acquisition Boards, Logic Analyzer, Signal Generator and High-Speed Oscilloscope. ■ Creating Design and Verification Datasheet and Specification. From June 2005 to September 2005 (4 months) TA @ From 2000 to 2005 (5 years) Design Engineer @ ■ Summer Internship in the Research and Development Department. ■ Design, Modeling, Implementation, and Functional Verification of an MII Interface for MAC Layer of HomePLUG IC project in Verilog using MentorGraphics ModelSim and Exemplar-Leonardo, Xilinx Foundation Series. ■ Design and Modeling of an RC4 Encryption Module for MAC Layer of HomePLUG IC project in VHDL using MentorGraphics ModelSim. ■ Creating Design and Verification Datasheet and Specification. From July 2001 to August 2001 (2 months) Network Administrator @ ■ Design, Develop, and Maintenance of an Internet Service Provider (ISP) for the Cooperating Companies and Branches. From April 2000 to August 2000 (5 months) Design Engineer @ ■ Member of the Research and Development Department. ■ Design, Modeling, Implementation, and Functional Verification of a Pipelined Datapath for UTS-DSP joint-project, a CISC DSP Processor Based on TI DSP TMS320C54x Architecture in VHDL using MentorGraphics ModelSim, Exemplar-Leonardo Spectrum Synthesis Tool, L-Edit Layout Tool on FPGA Flex10K250. ■ Functional Verification of UTS-DSP joint-project in VHDL using MentorGraphics ModelSim. ■ Creating UTS-DSP Design and Verification Datasheet and Specification. From September 1997 to August 2000 (3 years)

PhD, Electrical and Computer Eng. @ Northeastern University From 2000 to 2012 M.Sc., Computer Engineering (Computer Architecture) @ University of Tehran From 1996 to 1999 B.Sc., Computer Engineering (Software) @ Isfahan University From 1990 to 1996 Diploma, Mathematics and Physics @ Kharazmi (Mofateh) HighSchool From 1986 to 1990 Pedram Riahi is skilled in: VHDL, Perl, Matlab, SystemVerilog, SystemC, HTML, Assembly Language, Verilog, FPGA, Simulations, ModelSim, ASIC, C, C++, TCL, Algorithms, EDA, Electrical Engineering, Debugging, Semiconductors, Linux, Xilinx, Electronics, SoC, VLSI, Unix, Hardware Architecture, PCB design, RTL design, Software Engineering, Programming, Integrated Circuit..., Testing, IC, Microcontrollers, Software Development, Circuit Design, Microprocessors, Windows, Digital Signal..., Cadence Virtuoso, ClearCase, Computer Architecture, Digital Electronics, Digital Signal..., Functional Verification, Labview, Logic Synthesis, Processors, SPICE