Bachelor of Engineering (BE), EEE @
Birla Institute of Technology and Science, Pilani, India
Partha Kundu is working on networking problems dealing with scale - currently in high performance (Exascale) computing and in the recent past, on cloud infrastructures and security appliances. Throughout his career Partha has worked on the cutting edge of technology: from the design of the very first superscalar Intel Pentium processor chip to the architecture of the
Partha Kundu is working on networking problems dealing with scale - currently in high performance (Exascale) computing and in the recent past, on cloud infrastructures and security appliances. Throughout his career Partha has worked on the cutting edge of technology: from the design of the very first superscalar Intel Pentium processor chip to the architecture of the revolutionary Itanium instruction set to the highest performing DEC Alpha microprocessors.
As a hands-on technologist he brings experience working with nascent and emerging technologies as well as the ability to develop a view of relevant technology trends and communicate them in the form of a clear, convincing vision and roadmap. He is recognized as one of the earliest contributors to the field of on-chip interconnects, working within the broader community to find a scalable approach to the problem of communication within many core CPUs. Partha Kundu is an engineer and respected thought leader with a strong portfolio of publications, patents, and recognition from leading industry organizations and academia.
• Technology evangelism within company and across industry/academia
• Architect of high-performance x86, Itanium, and DEC/Alpha server CPUs
• Interconnection network analysis and design (Juniper Clos-based Qfabric)
• Ethernet and extensions for the data center (CEE)
• Multi-processor cache design (Intel Tukwila)
• Network-on-Chip (NoC) expertise
• Expert in component-level performance modeling and performance projection (C, C++, SystemC)
• Experience with high performance logic design (System Verilog, VCS/ModelSim)
• Expertise in power, power management for 65, 32nm CMOS processes
Skills & Expertise:
Architecture definition, Performance modeling, Cache design, Shared Memory, Interconnection networks, Microprocessors, SoC, Design flow, Low power design, RTL, ASIC, Verilog, micro architecture, Low-power Design, X86, ARM
Technical Director, Architect @ ARM based high performance microprocessor architecture for HPC and data center applications. Focus on high performance NIC & fabric architectures, low latency inter-node messaging. From June 2014 to Present (1 year 7 months) Sr. Distinguished Engineer, Corporate CTO office @ ASIC architecture, Security platform, data center fabric architecture.
• Architecture definition of next generation industry leading ASIC chip set for converged core and data center offerings. Low latency over large scale ethernet based networks, fabric congestion management.
• Developed an alternative security hardware platform (next gen SRX5000 platform) using commodity X86 CPUs and purpose built ASIC for power/performance advantage.
• Developed performance model to study and propose improvements for Juniper’s very large data center fabric chip set (Qfabric/DCF3.0). From February 2010 to May 2014 (4 years 4 months) Architect/Researcher @ Many core technology development, server & Database workload characterization:
• Developed high performance, low power on-chip interconnection network for many core high performance x86 CPUs.
• Developed (earliest published) hardware support to accelerate Transaction Memory (Hybrid TM)
• Cache and memory bandwidth management scheme for many core CPUs
• Database workload characterization (Oracle 10i in TPCC/E)
• Micro architecture exploration for first Intel Multi core CPU (Tanglewood/Tukwila) From 2001 to February 2010 (9 years) Consulting Engineer, Architect @ Principal Architect (memory system) of (EV8) Alpha micro-processor
• co-developed performance model
• uarch of load/store, data cache unit for industry's first OOO/SMT processor
• RTL design From 1996 to 2001 (5 years) Architect & Design Engineering manager @ • Architect definition team of Itanium Instruction Set Architecture (ISA)
• Design manager for first Itanium microprocessor
• Principal micro-architect (Bus system) of Itanium microprocessor
• Design engineer on first Pentium(tm) microprocessor From 1990 to 1996 (6 years) Hardware Engineer @ ASIC designer From 1987 to 1990 (3 years)
MS, Electrical Engineering @ Stony Brook University From 1985 to 1987 Bachelor of Engineering (BE), EEE @ Birla Institute of Technology and Science, Pilani, IndiaSt Columba's High School, N Delhi, India Partha Kundu is skilled in: Performance Engineering, Interconnect, Computer Architecture, Microprocessors, Microarchitecture, Processors, SoC, Logic Design, ASIC, Verilog, RTL design, VLSI, Embedded Systems, High Performance Computing, Hardware Architecture