Nirav Patel’s Email & Phone

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Nirav Patel

Senior ASIC/RTL Design Engineer @ Intel Corporation

Nirav Patel Contact Details

Location:
San Francisco Bay Area
Work:
Senior ASIC/RTL Design Engineer @ Intel Corporation
Component Debug Engineer @ Intel Corporation
Physical Design Engineer @ Intel Corporation
Education:
Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering @ Gujarat University
About:

I would like to expand my experience and knowledge in the field Embedded System and VLSI System designs and Post-Silicon Debug/Verification. Worked on many project based on VHDL,Verilog and C. Specialties: VHDL,Verilog, Simulation tools,Cadence Schematic and Layout Tools, C, Digital Circuit Testing, Synopsys tools,perl,unix scripting.

SILICON ARCHITECTURE ENGINEER @ -Working with Architects on feature evaluation for the next 

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