Involved in design implementation, project management and Technical trainings. Managing teams of design engineers working on client designs. Expert in design implementation from RTL to GDSII, particularly Timing Closure, Clock Tree Synthesis and LP checks.

Senior Engineering Manager @ From September 2014 to Present (1 year 4 months) Bengaluru Area, IndiaSenior Technical Manager @ From October 2012 to September 2014 (2 years) Physical Design Manager @ From July 2011 to September 2012 (1 year 3 months) Technical Manager @ From December 2010 to July 2011 (8 months) Staff Research Engineer @ From June 2008 to December 2010 (2 years 7 months) Lead Engineer @ From June 2005 to May 2008 (3 years) Associate Design Engineer @ From October 2001 to June 2005 (3 years 9 months) Trainee Engineer @ From July 2001 to October 2001 (4 months) Noida Area, India

MSc (Engg.), VLSI System Design @ Coventry University From 2009 to 2015 Diploma, Electronics and Communication Engg. @ Fr. Agnel Polytechnic From 1998 to 2001 Navyug From 1992 to 1998 Naveen Mudgil is skilled in: Clock Tree Synthesis, Physical Design, ASIC, Timing Closure, Power Analysis, Static Timing Analysis, TCL, SoC, Physical Verification, VLSI, LVS, Integrated Circuit Design, Microprocessors, Formal Verification, Primetime