ASIC Frontend - Digial FPGA Design

Design Engineer maXTouch @ Design, simulation and verification (SV, UVM, Assertions) Contributed in building UVM framework from scratch (Environment, UVCs, Interfaces) UVM Verification (Scoreboard, sequences and tests) Co-simulation using fineSim Netlist simulations From November 2013 to Present (2 years) Trondheim Area, NorwayDigital IC Design Engineer @ Working with a team of Analog/RF engineers for a Mixed-signal ASIC using 130 nm CMOS technology Specification, Design, Implementation and Verification of blocks using Verilog HDL Synthesis using RTL compiler and post synthesis verification PnR using Encounter and post PnR verification DRC and LVS of final Layout Behavioral modeling of analogue components in Verilog HDL From August 2011 to October 2013 (2 years 3 months) Berlin Area, GermanyFPGA Designer @ Design, Implementation and verification of Blocks for Digital Satellite Receiver. Components worked on • Automatic Gain Control – Generalized architecture supporting 8 to 14 bit ADC • Sample Interleaved poly-phase Numerically Controlled Oscillators for up/down conversion • Decimation Filter – One hardware architecture handling four carriers and support decimation factor from 1 to 80 • Matched filtering – One architecture for filtering four carriers • Pulse shaping Filter – Supporting all modulation schemes for DVB-S2 (BPSK, QPSK, 8PSK, 16APSK, 32APSK, 16QAM) • Detector – Support demodulation of all modulation schemes for DVB-S2 (BPSK, QPSK, 8PSK, 16APSK, 32APSK, 16QAM) • Reed Muller Encoder & Decoder From December 2009 to December 2010 (1 year 1 month) M.S (System-On-Chip) @ Masters in System on Chip Design From September 2008 to August 2010 (2 years)

A1.1, A1.2, Deutsch Course @ Volkshochschule Berlin Mitte From 2012 to 2012 M.S - System on Chip, Hardware Engineer @ Lund University From 2008 to 2010 Bachelor degree, Computer Systems Engineering @ North West Frontier Province University of Engineering and Technology From 2004 to 2008 Nadir Khan is skilled in: ModelSim, Verilog, VHDL, Xilinx, FPGA, ASIC, NCSim, Quartus, Xilinx ISE, Digital Signal..., Logic Synthesis, SoC, Perl, Verilog-A, Signal Processing, RTL design, Altera Quartus, Altera, CMOS, Shell Scripting, Encounter, Mixed Signal, NC-Verilog, Logic Analyzer, UVM, Functional Verification, RTL Design