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Mehrdad Reshadi

Principal Software Engineer / Architect

Principal Software Engineer / Architect at Instart Logic

Sunnyvale, California

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Mehrdad Reshadi's Email Addresses & Phone Numbers

Mehrdad Reshadi's Work Experience

Instart Logic

Principal Software Engineer / Architect

February 2014 to Present

Instart Logic

Software Engineer

February 2013 to Present

Qualcomm Research Silicon Valley

Sr. Staff Engineer, Manager

April 2012 to February 2013

Mehrdad Reshadi's Education

University of California, Irvine

PhD Information and Computer Science

2001 to 2007

University of Tehran

MSc Computer Engineering

1997 to 2000

Sharif University of Technology

BSc Computer Engineering

1993 to 1997

Mehrdad Reshadi's Professional Skills Radar Chart

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Perceptive
Resourceful
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52% Left Brained
48% Right Brained

Mehrdad Reshadi's Estimated Salary Range

About Mehrdad Reshadi's Current Company

Instart Logic

Frequently Asked Questions about Mehrdad Reshadi

What company does Mehrdad Reshadi work for?

Mehrdad Reshadi works for Instart Logic


What is Mehrdad Reshadi's role at Instart Logic?

Mehrdad Reshadi is Principal Software Engineer / Architect


What is Mehrdad Reshadi's personal email address?

Mehrdad Reshadi's personal email address is r****[email protected]


What is Mehrdad Reshadi's business email address?

Mehrdad Reshadi's business email addresses are m****[email protected], and m****[email protected]


What is Mehrdad Reshadi's Phone Number?

Mehrdad Reshadi's phone (213) ***-*584


What industry does Mehrdad Reshadi work in?

Mehrdad Reshadi works in the Research industry.


About Mehrdad Reshadi

📖 Summary

More than 20 years of work experience in software/hardware development. Broad technical background in Web technologies, compilers, dynamic languages, EDA tools, processor simulators. See http://www.reshadi.com for more details and resume.Principal Software Engineer / Architect @ From February 2014 to Present (1 year 11 months) Software Engineer @ Helping revolutionize the way the Internet gets delivered From February 2013 to Present (2 years 11 months) Sr. Staff Engineer, Manager @ Technically leading and developing a new parallel JavaScript engine. From April 2012 to February 2013 (11 months) Staff Engineer @ Working on web technologies, parallel runtime, JIT compiler, Virtual Machines. From August 2008 to April 2012 (3 years 9 months) Graduate Research Assistant @ * Developed new No-Instruction-Set-Computer (NISC) technology for designing custom (application specific) processors or dedicated hardware accelerators. * Developed new compiler technology that combines traditional compiler techniques with High-Level Synthesis algorithms. It accepts programs written in ANSI C or a subset of CIL assembly in .NET. * Participated in development of the specification format for modeling a NISC processor as well as modeling a system consisting of multiple NISC processors. * Participated in development of a framework that integrates different NISC tools. It gets the model of a NISC processor plus the program C code or .NET assembly and generates different outputs including simulatable and synthesizable Verilog RTL of the whole system as well as different views of the status of pipeline used for debugging and evaluation of the results. * Developed a web-based interface for the NISC tool-set framework available at http://www.cecs.uci.edu/~nisc. From January 2004 to September 2007 (3 years 9 months) Graduate Research Assistant @ * Developed Reduced Colored Petri Net (RCPN) a very generic and intuitive formalism for modeling complex pipelined processors and generating very high performance cycle-accurate simulators. * Developed cycle-accurate simulators for StrongArm and XScale processors using RCPN. The generated simulator runs 15 times on average faster than the very popular SimpleScalar simulator for ARM. * Developed a concise template-based formalism for modeling instruction-set of processors and generating high performance instruction-set simulator. * Developed a new hybrid simulation technique that combined interpretive and compiled simulation algorithms. * Developed algorithms for: (a) compilation-time reduction, (b) general instruction-binary decoding, (c) and fast instruction execution utilizing partial evaluation and memory-access time reduction. * Developed instruction-set simulators for ARM and SPARC processors. From September 2001 to January 2004 (2 years 5 months) Chief Software Architect @ * One of the three key people who analyzed the business process of one of the biggest trading companies in the country. Extracted and formalized the workflow of different departments. * One of the three key people who designed a complex dynamic web-based collaborative system for automating the business process. The system could follow the individual steps of workflow, ask users to enter data on proper schedules, and produce both detailed and high-level reports. Workflow could be updated in the database. * Designed and developed an XML-based framework to help web developers program more efficiently. Being done in year 2000, many of the features of my framework were similar to what was later introduced in ASP.NET 2.0 in year 2006. * Participated in the design of database structure. * Managed and coordinated several programmers. From 1999 to 2001 (2 years) Graduate Research Assistant @ * Developed an extensible, platform-independent intermediate format for hardware description languages (HDLs) specifically VDHL and designed an integrated multi-format (Binary, XML, formatted text) file representations for it. The format was then used in other tools such as VHDL Compiler and VHDL Simulator in the group. * Developed several logic synthesis algorithms for converting the intermediate format to Boolean expressions and eventually gates. * Participated in the design and development of a compiled simulation of VHDL language. * Managed development of a generic Graphical Schematic Editor used for designing logic circuits. * Managed development of a generic Integrated Development Environment (IDE) used for integrating several tools that were developed in the CAD Lab by different researchers. * Coordinated the Simulation, Compiler and Synthesis groups in the CAD lab. * Implemented several fault tolerant architectural techniques in behavioral and structural VHDL. From 1998 to 2001 (3 years) Embedded Software Developer @ * Developed several real-time / reliable monitoring and control applications. * Developed an Axle Test Monitoring System for MEGA Motors Co (An automobile manufacturer). * Developed a CNC controlling software for a drilling machine in MEGA Motors Co. * Developed an Engine Test Monitoring System for SANE engine factory. * Developed a Drilling Machine Controller Software for SANE engine factory. From 1996 to 1999 (3 years) PhD, Information and Computer Science @ University of California, Irvine From 2001 to 2007 MSc, Computer Engineering @ University of Tehran From 1997 to 2000 BSc, Computer Engineering @ Sharif University of Technology From 1993 to 1997 Mehrdad Reshadi is skilled in: Algorithms, Compiler Optimization, Software Engineering, JavaScript, TypeScript, C#, C++, Computer Architecture, Programming, Content Delivery, C, Embedded Systems, Verilog, Software Development, Debugging


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Mehrdad Reshadi's Personality Type

Introversion (I), Sensing (S), Thinking (T), Perceiving (P)

Average Tenure

2 year(s), 7 month(s)

Mehrdad Reshadi's Willingness to Change Jobs

Unlikely

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Mehrdad Reshadi's Social Media Links

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