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Matthew Orsini

Design Verification Engineer @ EZchip

Senior Design Verification Engineer at NVIDIA

Providence, Rhode Island Area

Ranked #22 out of 441 for Design Verification Engineer in Rhode Island

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Matthew Orsini's Email Addresses & Phone Numbers

Matthew Orsini's Work Experience

EZchip

Design Verification Engineer

December 2015 to March 2016

Westborough, MA

Tufts Cummings School of Veterinary Medicine

ITS Intern

May 2010 to August 2010

NVIDIA

Senior Design Verification Engineer

Westborough, Massachusetts, United States

Matthew Orsini's Education

Worcester Polytechnic Institute

Master of Science (M.S.), Computer Engineering

2012 to 2015

University of Massachusetts Dartmouth

Bachelor of Science, Computer Engineering

2007 to 2011

Matthew Orsini's Professional Skills Radar Chart

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Purposeful
Structured
Introspective

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Based on our findings, Matthew Orsini is ...

56% Left Brained
44% Right Brained

Matthew Orsini's Estimated Salary Range

About Matthew Orsini's Current Company

EZchip

Frequently Asked Questions about Matthew Orsini

What company does Matthew Orsini work for?

Matthew Orsini works for EZchip


What is Matthew Orsini's role at EZchip?

Matthew Orsini is Design Verification Engineer


What is Matthew Orsini's personal email address?

Matthew Orsini's personal email address is ma****[email protected]


What is Matthew Orsini's business email address?

Matthew Orsini's business email address is m****[email protected]


What is Matthew Orsini's Phone Number?

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What industry does Matthew Orsini work in?

Matthew Orsini works in the Semiconductors industry.


Who are Matthew Orsini's colleagues?

Matthew Orsini's colleagues are Jolene Low, Ann Toh, Tirthankar Mitra, Vishal Bharat, Akiko Nakanaga, CPA, Charles Kim, Arik Zigelboim, Alex Kovshilovsky, Ori Golan, and Oren Duer


About Matthew Orsini

💼 Past Experience

Work experience with design verification:Senior Design Verification Engineer at NVIDIA in Westborough, Massachusetts, United States. Lead verification engineer for high-performance mesh interconnects in BlueField SoCs. Created coverage-driven functional testplans and constructed UVM-based testbenches to validate and achieve functional coverage targets for these complex SoCs. Drive full-chip verification effort by combining unit-level verification from several subsystems. Provide support and debug to emulation teams, including software and system-validation.Mentor incoming verification engineers to speed the learning curve. Provide feedback for validation best practices and techniques. ASIC Design / Verification Engineer at Seagate Technology from June 2011 to December 2015 (4 years 7 months) in Shrewsbury, MA. Design and verification of SystemVerilog and Verilog RTL blocks inside an ARM-based processor subsystem group targeting hard-disk drive and solid-state drive solutions. Engineering Maintenance Intern at Wyman Gordon from January 2010 to January 2010 (1 month) in Grafton, MA. Performed diagnostic analysis of a steel cutting machine by logging and analyzing PLC output data.


🎓 Education

Matthew Orsini has a Master of Science in Computer Engineering from Worcester Polytechnic Institute in 2015. His prior education was in Computer Engineering from the University of Massachusetts Dartmouth from 2007-2011. While at Worcester Polytechnic Institute, Mr. Orsini received the prestigious club award for his work in group project. Mr. Orsini's club work focused on developing a computer game that can be played on a router.


💡 Technical & Interpersonal Skills

Matthew Orsini has 5 years of experience in design verification, 5 years of experience in ARM engineering, 5 years of experience in software engineering, and 2 years of experience in system engineering. In addition, Matthew has additional experience in ASIC design and verification.


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Matthew Orsini's Personality Type

Introversion (I), Intuition (N), Thinking (T), Judging (J)

Average Tenure

1 year(s), 10 month(s)

Matthew Orsini's Willingness to Change Jobs

Unlikely

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