• 3+ year of significant Design Verification experience in Functional Verification of complex ASIC Designs • Significant Startup experience including tape out and feature releases • Strong knowledge of OOP concepts, System Verilog and UVM • Expert in analyzing regression failures and efficiently finding bugs in RTL • Quick at debugging using Waveforms and Log files • Familiar with Linux/Unix environment and revision control tools like SVN, CVS, AcuRev • Hands on experience in UVM register abstraction layer • Comprehensive knowledge of Constrained Random and Functional Coverage Driven Verification

Verification Engineer @ • Played active role in verification of the new feature and its release in SGN project. • Modified UVM Components such as master/slave driver, sequences and scoreboard for the Sonics fabrics’ verification. • Implemented concurrent assertion properties, general sequences and documented them as part of customer release. • Improved functional coverage by evaluating current coverage, writing new cover points and modifying stimulus. • Added functional cover groups and assertion properties to the RTL using Python scripting. • Responsible for maintenance of random/fixed configuration regression for all fabric components. • Documented the fabric component’s sequences for feature release. • Implemented procedural cover group in master driver. • Debugged issues related to sequences/functional coverage/assertion implementation and resolved bugs. • Added backdoor read support for configuration registers in RAL. • Evaluated code coverage holes using lint test results. From June 2015 to Present (7 months) Design Verification Engineer @ • Played a key role in tape out of next generation 10G® Wi-Fi chip project. • Created test plan for slave sub system. • Ported System Verilog based verification environment and wrote test cases to verify slave subsystem (I2C, UART, Timers, Watchdog Timer and GPIO) of SoC. • Developed test bench and test cases for the CQE (Control queuing Engine) interface which is responsible for exchange of information across the Processors. • Responsible for automation of execution/reporting of regressions and maintaining multiple regression suites. • Wrote C code, generated hex files and integrated Hex files in system Verilog tests verifying register read/writes through real cpu. • Verified the default value and access of all register space of chip through bfm read/write. • Worked on verification of debug bus feature for different blocks of the chip. • Designed the driver to select different Test modes of the chip through JTAG interface. • Developed test cases for HDP (Hardware data path) flow traffic. From October 2014 to May 2015 (8 months) Hardware VLSI Verification Engineer @ • Working on UVM based verification environment to verify SPI slave Interface of USB PD Type-C protocol SoC • Wrote UVM sequences for SPI layer • Developed Register abstraction layer for SPI and I2C for single and burst read/write • Developed module level test-bench environment for USB PD Type-C protocol SoC From May 2014 to October 2014 (6 months) ASIC Verification Intern @ • Verified PCIe DUT Endpoint and debugged through waveforms • Developed and debugged PCIe Gen3/Gen2/Gen1 System Verilog/UVM Test cases to verify PHY layer of PCIe End Point IP • Developed PCIe GEN3 SystemVerilog/UVM Test Cases to verify Transaction layer and Data Link Layer of IP • Involved in development of PCIe PHY layer test plan for LTSSM sub-states • Modified test plan for additional test case development • Added functional coverage cover points/bins for PCIe From April 2013 to May 2014 (1 year 2 months) ASIC Verification Trainee @ • Gained Intensive training in industry standard System Verilog and Verification Methodology UVM, Functional Verification, Test bench development, Shell and Perl Scripting, Code Coverage and Constrained Random Verification From January 2013 to May 2013 (5 months) Electrical Engineering Intern @ • Developed C program to reframe various data structure to different binary packets and used IDesignSpec for documentation • Debugged tests and created Perl script to extract yield information. • Generated timing diagrams and analyzed From May 2012 to August 2012 (4 months) Greater San Diego Area

Master's degree, Electrical, Electronics and Communications Engineering @ California State University-Fullerton From 2010 to 2013 Master's degree, Electrical and Electronics Engineering @ California State University-Fullerton From 2010 to 2013 Khushbu Akabari is skilled in: Verilog, VLSI, VHDL, FPGA, Matlab, SystemVerilog, Functional Verification, Perl, Debugging, Xilinx ISE, ASIC, Linux, UVM, PCIe, Perl Script